New Techniques to Reduce the Execution Time of Functional Test Programs

Gaudesi, Marco; Pomeranz, Irith; Reorda, M. Sonza; Squillero, Giovanni

doi:10.1109/tc.2016.2643663

Cited by 17 publications

(5 citation statements)

References 41 publications

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“…Computing these figures for a given STL also requires a new generation of tools called Functional Fault Simulators. Several recent works introduced guidelines on how to correctly generate STLs for CPUs [27], [28] and peripherals [29], how to speed up the FI experiments [30], how to maximize their fault coverage in the different scenarios (possibly minimizing the test time [31]), and how to re-use existing STLs.…”

Section: B Software Test Librariesmentioning

confidence: 99%

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Silva

Bagbaba

Ruospo

et al. 2020

2020 IEEE 38th VLSI Test Symposium (VTS)

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The current demands for autonomous driving generated momentum for an increase in research in the different technologies required for these applications. Nonetheless, the limited access to representative designs and industrial methodologies poses a challenge to the research community. Considering this scenario, there is a high demand for an open-source solution that could support development of research targeting automotive applications. This paper presents the current status of AutoSoC, an automotive SoC benchmark suite that includes hardware and software elements and is entirely open-source. The objective is to provide researchers with an industrial-grade automotive SoC that includes all essential components, is fully customizable, and enables analysis of functional safety solutions and automotive SoC configurations. This paper describes the available configurations of the benchmark including an initial assessment for ASIL B to D configurations.

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Section: B Software Test Librariesmentioning

confidence: 99%

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Silva

Bagbaba

Ruospo

et al. 2020

2020 IEEE 38th VLSI Test Symposium (VTS)

Self Cite

View full text Add to dashboard Cite

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“…In [16], the authors described multiple solutions adopted in real industry test cases. Similarly, some algorithms for automatically compacting existing test programs to reduce their size [17]- [19], or duration [20] have been recently proposed. In another work [21], the authors proved that formal techniques could be successfully adopted and used for in-field test program generation for pipelined processors.…”

Section: Related Work In the Areamentioning

confidence: 99%

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

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The highly parallel processing capabilities and reduced power performance of General Purpose Graphics Processing Units (GPGPUs) have been crucial factors for their massive use in multiple fields, such as multimedia and high-performance computing applications. Nowadays, more demanding areas, such as automotive, employ GPGPU devices where safety and reliability are mandatory design constraints. Nevertheless, the structural complexity, the transistor density, and the implementation in the latest silicon technologies introduce challenges to match safety and reliability requirements. In these technologies, wear-out and aging are factors that may significantly increase the occurrence of permanent faults during the lifetime operation. Moreover, these faults may generate unacceptable misbehaviors during the execution of an application. These constraints require devising new methods for in-field fault detection, thus verifying the integrity and correct behavior of the device during its whole operational life. This work proposes a technique to generate functional self-test programs targeting the detection of permanent static faults in the memory of the warp scheduler of a GPGPU. The proposed technique can translate fault primitives, which represent the effect of faults in a memory cell, into self-test functions and programs composed of a sequence of operations to excite the fault in the memory and to propagate its effects to a visible location, thus detecting its presence. We focused on the memory in the warp scheduler because it represents a crucial module for the device operation. Furthermore, this memory is present in each Streaming Multiprocessor (SM) of a GPGPU. Some experimental results to validate the method have been gathered, resorting to the NVIDIA Visual Profiler and the Nsight Debugger using the NVIDIA-GEFORCE GTX GPU platform and a structural fault simulator. The CUDA programming environment was used to implement the test procedures. INDEX TERMS Functional test, general purpose graphics processing units (GPGPUs), memory test, software-based self-test (SBST).

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“…In conventional SBST methods, the whole test program is required to be executed at once [35][36][37]. Execution of a test program assuming that the test program is stored in the cache memory takes a processing core several thousand cycles.…”

Section: Test Snippet and Segmented Test Applicationmentioning

confidence: 99%

HASTI: hardware‐assisted functional testing of embedded processors in idle times

Kamran

2019

IET Computers & Digital Techniques

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In the past decades, software-based self-testing (SBST) which is testing of a processing core using its native instructions has attracted much attention. However, efficient SBST of a processing core which is deeply embedded in a multicore architecture is still an open issue. In this study, inspiring from built-in self-test methods, the authors place several number of hardware test components next to the processing cores in order to overcome existing SBST challenges. These test components facilitate quick testing of embedded cores by providing several mechanisms such as virtual fetch, virtual jump, fake load & store, and segmented test application. In order to enable segmented test application, they propose the concept of test snippet and a test snippet generation approach. The result is the capability of testing embedded cores in short idle times leading to efficient online testing of the cores with zero performance overhead. The authors' results show that their test snippet generation approach not only leads to the production of test snippets which are properly fitted the proposed test architecture but also its final fault coverage is comparable and even a little better than the fault coverage of the best existing methods.

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New Techniques to Reduce the Execution Time of Functional Test Programs

Cited by 17 publications

References 41 publications

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

HASTI: hardware‐assisted functional testing of embedded processors in idle times

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