New symmetric and planar designs of reversible full-adders/subtractors in quantum-dot cellular automata

Abstract

Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, promising alternative to CMOS technology due to faster speed, smaller size, lower power consumption, higher scale integration and higher switching frequency. Also, power dissipation is the main limitation of all the nano electronics design techniques including the QCA. Researchers have proposed the various mechanisms to limit this problem. Among them, reversible computing is considered as the reliable solution to lower the power dissipation. On the other hand, adders are fundamental circuits for most digital systems. In this paper, Innovation is divided to three sections. In the first section, a method for converting irreversible functions to a reversible one is presented. This method has advantages such as: converting of irreversible functions to reversible one directly and as optimal. So, in this method, sub-optimal methods of using of conventional reversible blocks such as Toffoli and Fredkin are not used, having of minimum number of garbage outputs and so on. Then, Using the method, two new symmetric and planar designs of reversible full-adders are presented. In the second section, a new symmetric, planar and fault tolerant five-input majority gate is proposed. Based on the designed gate, a reversible full-adder are presented. Also, for this gate, a fault-tolerant analysis is proposed. And in the third section, three new 8-bit reversible fulladder/subtractors are designed based on full-adders/subtractors proposed in the second section. The results are indicative of the outperformance of the proposed designs in comparison to the best available ones in terms of area, complexity, delay, reversible/irreversible layout, and also in logic level in terms of garbage outputs, control inputs, number of majority and NOT gates.

A Novel Reversible Hybrid Crossover-Based Efficient 3D Adder-Subtractor Design Using QCA Spin Technique

“…There are also some existing works related to our proposed design, such as: In 2017, Moein Kianpour et al presents a full addersubtractor design by using reversible QR gate to reduce the occupied area, latency, and energy dissipation of proposed circuit [12]. But, the given parameters of this paper [12] are optimized more by using a combination of majority voter gate and reversible modified Feynman gate [13] [14] using coplanar crossing, which also reduces the area, cell complexity, and latency of proposed design. These all parameters are again optimized using multilayer crossing (3 layers) in 2020's published paper [15] and 2021's published paper [16], written by Mostafa Sadeghi et al and Mukesh Patidar et al, respectively.…”

QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology

“…After that time, various types of combinational and sequential representations are experimented in this "QCA" platform till now. There are also various types of "QCA" based designs on full-adder, fullsubtractor or full-adder-subtractor are already published in different articles in different years [9][10][11][12][13][14][15] and the parametricoptimization of proposed component is rapidly increased in last few years. In 2017, Barughi and Heikalabad presented a "Full Adder/Subtractor" design using 90 quantum cells in a multilayer 3D platform, where 3 layers are required with 0.6 µm 2 area and 1.5 clock-cycle delay [11] and this occupied area (0.14 µm 2 ) and delay (1.25 clock-cycle) are reduced by Firdous Ahmad et.al in the next year, where the reversible gates (3:3 New Reversible Gate and Modified Feynman Gate) are used to design the published structure with proper powerdissipation calculation.…”

“…In our proposed full-adder-subtractor design, the device-occupiedarea, delay, energy-dissipation and quantum-cost are minimized compare to other previous published structures. The cell-count of proposed circuit is reduced more by Moein Sarvaghad-Moghaddam et.al in 2019 [14], which is formed to design 8 bit reversible "Adder/Subtractor" design. In that above design, 2 to 1 MUX is added with reversible "Adder-Subtractor" design and in this paper the presented single-bit reversible "Adder-Subtractor" design is compared with our proposed multilayer reversible "Adder-Subtractor" design, which ultimately gives a multilayer multi-bit (4-bit) "Adder-Subtractor" design based on the combination of RCA and RBS (hybrid formation).…”

“…In that above design, 2 to 1 MUX is added with reversible "Adder-Subtractor" design and in this paper the presented single-bit reversible "Adder-Subtractor" design is compared with our proposed multilayer reversible "Adder-Subtractor" design, which ultimately gives a multilayer multi-bit (4-bit) "Adder-Subtractor" design based on the combination of RCA and RBS (hybrid formation). In that "Adder-Subtractor" design of paper [14], 48 cells quantum cells are required, where the occupied area is 0.039 µm 2 and delay is 3 clock-zone and 2 garbage outputs are present in that proposed design which is reduced in our design by using them as the inputs of fullsubtractor. These parameters are again optimized in next year down to 38 cells, 0.03 µm 2 area and 0.5 clock-cycle (2 clockzone) delay by Mostafa Sadeghi, Keivan Navi et.al [15] in multilayer platform with proper energy dissipation calculation.…”

Synthesis of Silicates for High-Performance Oxide Semiconductors: Electronic Structure Analysis

“…The demand for new approaches in the information technology industry is increasingly fueled by the fundamental limitations arising from the constantly ongoing miniaturization of current semiconductor devices . Novel concepts, such as the recently proposed quantum cellular automaton, follow schemes complementary to pervasive current-based architectures by exploiting the quantum nature at the molecular or atomic scale.…”