New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory

Zhu, Ming; Yi, Xiao Li; Wei, Luo

doi:10.1109/vlsisoc.2011.6081647

Cited by 25 publications

(3 citation statements)

References 13 publications

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“…The proposed technique can be used to protect any block binary error correction code that uses a syndrome comparison based decoder. Therefore, it can be used for example for SEC [3], SEC-DED [4], SEC-DAEC [5], [6] or three bit burst [9], [10] codes. This means that the proposed technique would be applicable to most error correction codes currently used to protect memories.…”

Section: Correction Masking Protectionmentioning

confidence: 99%

“…For example, Single Error Correction (SEC) [3] and Single Error Correction Double Error Detection (SEC-DED) [4] codes are commonly used to protect against single bit errors. However, as technology scales, Multiple Cell Upsets (MCUs) that affect nearby memory cells become more prominent [1] and codes that can correct double adjacent errors [5], [6] or larger burst of errors [7], [8], [9], [10] are also becoming popular.…”

Section: Introductionmentioning

confidence: 99%

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Correction Masking: A Technique to Implement Efficient SET Tolerant Error Correction Decoders

Liu

Reviriego

Argyrides

et al. 2022

IEEE Trans. Device Mater. Relib.

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Single Event Transients (SETs) can be a major concern for combinational circuits. Its importance grows as technology scales because a small charge can create a large disturbance on a circuit node. One example of circuits that can suffer from SETs is the decoders of the Error Correction Codes (ECCs) that are used to protect memories from errors. This paper presents Correction Masking (CM), a technique to implement SET tolerant syndrome decoders. The proposed technique is presented and evaluated both in terms of protection effectiveness and circuit overhead. The results show that it can provide an effective protection while reducing the circuit area and power significantly compared to a Triple Modular Redundancy (TMR) protection. An interesting result is that Correction Masking also reduces the delay as it adds less logic in the critical path than TMR. Finally, the proposed technique can be used for any syndrome decoder. This means that it is applicable to many of the ECCs used to protect memories such as Single Error Correction (SEC), Single Error Correction Double Error Detection (SEC-DED), Single Error Correction Double Adjacent Error Correction (SEC-DAEC), and 3-bit burst codes.

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Section: Correction Masking Protectionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Correction Masking: A Technique to Implement Efficient SET Tolerant Error Correction Decoders

Liu

Reviriego

Argyrides

et al. 2022

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

show abstract

“…Currently, ECCs with single error correction and double errors detection (SEC-DED) capabilities are widely used in the memory industry. However, as multi-bit error increases in NVMs, SEC-DED codes may fail [22]. In this scenario, advanced ECCs with multi-bit error correction capability are preferable, which, however, add great complexity to the memory system.…”

Section: Introductionmentioning

confidence: 99%

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

Liu

Zhang

et al. 2017

IEICE Electron. Express

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Non-volatile memories (NVMs), such as Magnetic RAM and Resistive RAM, have been considered as the potential working or storage memories in the next generation computer architectures, thanks to the various merits, such as non-volatility, low power and high speed etc. However, new technology brings simultaneously new challenges, e.g. reliability issue, before practical applications. Compared with conventional memories, the errors in NVMs are generally asymmetric, resulting in different failure rates for 0-1 and 1-0 bit flipping. Error correcting codes (ECCs) are common solutions for protecting memories from errors. The most widely used ECCs are the single error correction and double error detection (SEC-DED) codes. Unfortunately, they are primarily designed for correcting symmetric errors and their error correction capabilities are limited to only one bit. Regarding the failure characteristics (e.g., multi-bit and asymmetric) of NVMs, conventional SEC-DED codes are not efficiently applicable. This paper proposes an extended coset decoding scheme for NVMs. Our simulation results with a Hamming code (with Hamming distance of only three) as an example show the effectiveness of the proposed decoding scheme. The proposed decoding scheme can also be extended to other linear block codes and is rather suitable for scenarios with multi-bit asymmetric error features.

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