New reliability assessment method for solder joints in BGA package by considering the interaction between design factors

Abstract

Abstract-As the integration and the miniaturization of electronics devices, design space become narrower and interactions between design factors affect their reliability. This paper presents a methodology of quantifying the interaction of each design factor in electronics devices. Thermal fatigue reliability of BGA assembly was assessed with the consideration of the interaction between design factors. Sensitivity analysis shows the influence of each design factor to inelastic strain range of a solder joint characterizing the thermal fatigue life if no interaction occurs. However, there is the interaction in BGA assembly since inelastic strain range depends on not only a mismatch in CTE but also a warpage of components. Clustering can help engineers to clarify the relation between design factors. The variation in the influence was taken to quantify the interaction of each design factor. Based on the interaction, simple evaluating approach of inelastic strain range for the BGA assembly was also developed. BGA package was simplified into a homogeneous component and equivalent CTE was calculated from the warpage of BGA and PCB. The estimated equation was derived by using the response surface method as a function of design factors. Based upon these analytical results, design engineers can rate each factor's effect on reliability and assess the reliability of their basic design plan at the concept design stage.

Impact of Mold Properties on the Reliability of Ball Grid Array Packaging

“…An electronic package has many parts and properties (see Figure 1). The literature has many examples on the influence of materials properties, physical dimensions and configurations (9,10). In this work, the influence of material properties of the mold and its thickness are investigated.…”

Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

“…Therefore, the CTE mismatch between the solder layer and the upper copper layer in model III was larger than the state in model II. In other words, the DBC substrate limited the deformation of the solder layer more strongly than the individual copper layer, and it could more significantly reduce the CTE mismatch between the chip and the solder layer [35,36]. This was evidenced by the fact that the maximum σ Q value in model III (Figure 7B) was lower than the maximum σ N value in model II (Figure 5B).…”