“…1 In the case of a next-generation silicon-on-insulator (SOI) wafer, the thickness distribution of the top thin silicon layer should have a peak-to-valley (P-V) value of less than 1.0 nm over the entire surface of a 450-mm wafer. 2 Deterministic processing methods, such as ion beam figuring (IBF), 3,4 numerically controlled (NC) elastic emission machining (EEM), 5 plasma jet machining (PJM), 6,7 electrical discharge machining (EDM), 8,9 NC plasma chemical vaporization machining (PCVM), [10][11][12] local wet etching (LWE), 13 NC sacrificial oxidation, 14,15 and others, have been developed to achieve such accuracy. Although the processing mechanisms of these machining methods differ, they all consist of two components: a processing head that can process small areas, ranging in diameter from approximately the sub-millimeter range to several millimeters and an X-Y table system that enables the processing head to scan the whole area of a workpiece at a controlled feed speed.…”