New power gated SRAM cell in 90nm CMOS technology with low leakage current and high data stability for sleep mode

Meena, Naresh Kumar; Joshi, Amit M.

doi:10.1109/iccic.2014.7238333

Cited by 6 publications

(1 citation statement)

References 18 publications

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“…It is also the emerging task to design the intermediate processing devices with low power dissipation. In order to overcome these challenges, a novel design is proposed of differential amplifier using MOS configuration [3]. The purpose of this design is to provide precise and accurate data of signal with low power consumption and good signal quality (that is low noise) [4].…”

Section: Introductionmentioning

confidence: 99%

Design of Two-Stage Differential Amplifier with Stacked Transistors for Biomedical Applications

Jain¹,

Sharma

Joshi

2021

Preprint

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In this paper, CMOS based optimized two stage differential amplifier circuit for convenient biomedical signal conditioning system is presented. A low-power, low noise & high CMRR differential amplifier is designed for portable ECG signal conditioning using MOS based low pass filter with stacked transistors. The stack transistors with MOS which is connected at output terminal optimize the design for ECG signal conditioning and other biomedical device signal conditioning. The presented amplifier is designed with standard 45nm CMOS process technology at a 0.85 V supply voltage. The simulation results are derived using Cadence Analog Virtuoso Spectre Simulator. The simulation results show that the presented differential amplifier has a common-mode rejection ratio (CMRR) of 178dB at 100Hz, power supply rejection ratio (PSRR) of 68 dB and power dissipation of 1.5μW. The input referred (IR) noise is 3.83μV/√f and slew rate is 11volt/μsec. These obtained performance parameters is better and efficient compared to conventional differential amplifier. The noise performance is improved using proposed design compared to previous designed differential amplifier.

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Section: Introductionmentioning

confidence: 99%