New placement prediction and mitigation techniques for local routing congestion

Taghavi, Taraneh; Li, Zhuo; Alpert, Charles J.; Nam, Gi-Joon; Huber, Andrew D.; Ramji, Shyam

doi:10.1109/iccad.2010.5654225

Cited by 53 publications

(41 citation statements)

References 7 publications

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“…The key idea is that pinto-pin interference needs to be explicitly considered during pin accessibility evaluation. The similar idea applies to both intracell and inter-cell pin accessibility evaluation at the placement stage [58], [68].…”

Section: Definition 1 (Hit Point) the Overlap Of An M2 Routing Track mentioning

confidence: 99%

“…Standard cell designers can address this issue by I/O pin optimization with the assistance from pin access optimization and evaluation engine [63], [72]. A detailed placement engine can mitigate routing resource competitions by intelligent cell spreading [58]. Global routing can benefit routing closure by accurate modeling of local pin access impact on routing resources.…”

Section: Pin Access and Routing Co-optimizationmentioning

confidence: 99%

“…The complexities of cell coloring, inter-cell pin accessibility and other manufacturing constraints interfere with each other, which makes it difficult to predict the appropriate spacing among standard cells [19], [58]. Advanced placement engine is needed to properly allocate white space among standard cells for better design closure.…”

Section: Conclusion and Future Directionmentioning

confidence: 99%

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Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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Abstract:In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability. The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques. Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools. However, unidirectional layout style introduces significant impacts on the physical design flow. Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture. In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure. Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints. In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

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Section: Definition 1 (Hit Point) the Overlap Of An M2 Routing Track mentioning

confidence: 99%

Section: Pin Access and Routing Co-optimizationmentioning

confidence: 99%

Section: Conclusion and Future Directionmentioning

confidence: 99%

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Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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“…This method first finds amount of free space around the current cell that is needed to accommodate the size change, and computes the required movements of the current cell and neighboring cells. This provides three pieces of information that are used to find the approximate (ĉ area ): 2 -m 1 : Number of dislocated pins -m 2 : Utilized area over pin bounding box (over all layers) -m 3 : The routing cost (from [Taghavi et al 2010]). …”

Section: Eco Costmentioning

confidence: 99%

“…The cost m 3 is a measure of the routability of a library cell called the cell cost [Taghavi et al 2010], and is defined as:…”

Section: Eco Costmentioning

confidence: 99%

ECO cost measurement and incremental gate sizing for late process changes

Lee

Gupta

2013

ACM Trans. Des. Autom. Electron. Syst.

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Changes in the manufacturing process parameters may create timing violations in a design, making it necessary to perform an Engineering Change Order (ECO) to correct these problems. We present a framework to perform incremental gate sizing for process changes late in the design cycle, and a method to create initial designs that are robust to late process changes. This includes a method to measure and estimate ECO cost, and to transform these costs into linear programming optimization problems. In the case of ECOs, on average, the method reduces ECO costs by an average of 89% in changed area compared to a leading commercial tool. Furthermore, the robust initial designs are, on average, 55% less likely to need redesign in the future.

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Standard Cell Compliance and Placement Co-Optimization

Pan

2016

Design for Manufacturability With Advanced Lithography

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New placement prediction and mitigation techniques for local routing congestion

Cited by 53 publications

References 7 publications

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Toward Unidirectional Routing Closure in Advanced Technology Nodes

ECO cost measurement and incremental gate sizing for late process changes

Standard Cell Compliance and Placement Co-Optimization

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