New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Cao, Yu; Satō, Takashi; Orshansky, Michael; Sylvester, Dennis; Hu, Chenming

doi:10.1109/cicc.2000.852648

Cited by 376 publications

(197 citation statements)

References 4 publications

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“…Both designs were simulated using hspice with realistic transistor models from [8]. Apart from the minimum sized two input gates, the use of shift registers and associated flip flops for data buffering presents a significant problem because the flip flops fail to function below the threshold voltage.…”

Section: Resultsmentioning

confidence: 99%

“…To the best of our knowledge, no explicit investigation of obtaining V optimal and the minimum energy point for different adder topologies in the context of subthreshold design has been reported. We examine four adder circuits: Carry Look Ahead(CLA), Ripple Carry(RC), Carry Select(CS) and Carry Skip(CSK), for which minimum energy point is determined, using 0.13µ Berkeley Predictive Technology Models [8]. Fig.2 shows hspice simulation of the minimum energy point analysis of the adders as a function of V dd .…”

Section: Minimum Energy Point Analysis Of Addersmentioning

confidence: 99%

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Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Mishra

Al-Hashimi

2009

Lecture Notes in Computer Science

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Abstract. Subthreshold design has been proposed as an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. In this paper we propose a subthreshold FIR architecture which brings the benefits of reduced leakage energy, reduced minimum energy point, reduced operating voltage and increased operating frequency when compared with recently reported subthreshold designs. We shall demonstrate this through the design of a 9-tap FIR filter operating at 220mV with operational frequency of 126kHz/sample consuming 168.3nW or 1.33pJoules/sample. Furthermore, the area overhead of the proposed method is less than that of the transverse structure often employed in subthreshold filter designs. For example, a 9-tap filter based on transverse structure has 5× higher area than the filter designed using our proposed method.

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Section: Resultsmentioning

confidence: 99%

Section: Minimum Energy Point Analysis Of Addersmentioning

confidence: 99%

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Mishra

Al-Hashimi

2009

Lecture Notes in Computer Science

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“…The gate sizes were then used with SPICE 70nm models [7] to compute the delays of the circuits for the 70nm technology. All the gates had a transistor channel length of 70nm, V DD of 1V and V th of 0.2V.…”

Section: Resultsmentioning

confidence: 99%

“…Figures 1 and 2 show SPICE simulation results for generated glitch width and propagated glitch width, respectively, for an inverter for different values of gate size, gate channel length, gate supply voltage (V DD ) and gate threshold voltage (V th ). The SPICE models are for 70nm technology node [7]. The minimum and maximum values of the variables are indicated on the x-axis.…”

Section: Glitch Tolerance Characteristics Of Individual Gatesmentioning

confidence: 99%

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

Dhillon

Diril

Chatterjee

2008

Design, Automation, and Test in Europe

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“…The comparison between the BISER FFs and other soft-error-tolerant FFs were demonstrated in [14] and thus not shown in this paper. The evaluated FFs are designed on a 45 nm predictive technology model [15]- [18] and simulated by HSPICE. The V DD supply voltage and temperature are set to 1.0 V and 27…”

Section: Reconfigurable C-elementmentioning

confidence: 99%

Construction of BILBO FF with Soft-Error-Tolerant Capability

Namba

Ito

2011

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, a soft-error-tolerant BILBO (Built-In Logic Block Observer) FF (flip-flop) is presented. The proposed FF works as a soft-error-tolerant FF in system operations and as a BILBO FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft-error-tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF. The proposed FF contains a reconfigurable C-element with XNOR calculation capability, which works as a C-element for soft-errortolerance during system operations and as an XNOR gate employed in linear feedback shift registers (LFSRs) during manufacturing testing. The evaluation results shown in this paper indicate that the area of the proposed FF is 8.5% smaller than that of a simple combination of the existing BISER and BILBO FFs. In addition, the sum of CLK-Q delay and D-CLK setup times on system operations for the proposed FF is 19.7% shorter than that for the combination. key words: soft-error-tolerance, DFT (design for test), BISER (built-in soft-error resilience), BILBO (built-in logic block observer), reconfigurable C-element

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New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation

Cited by 376 publications

References 4 publications

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

Construction of BILBO FF with Soft-Error-Tolerant Capability

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