New optimal error-correcting codes for crosstalk avoidance in on-chip data buses

Abstract

Codes that simultaneously provide for low power dissipation, crosstalk avoidance, and error correction in the ultra deep submicron/nanometer VLSI fabrication, were recently introduced by Chee et al. in 2015. Such codes were revealed to be closely related to balanced sampling plans avoiding adjacent units, which are widely used in the statistical design of experiments. In this paper, we construct a new family of optimal codes with such properties, by determining the maximum size of packing sampling plans avoiding certain units.

Improved asymptotically optimal error correcting codes for avoidance crosstalk type-IV on-chip data buses

“…It is easy to check that the lower bound B(n, 3; 2) + ⌊ n−1 2 ⌋ for an (n, 4, 3)-IV code in Lemma 1 coincides with B(n) and B(n) − 1 for each odd order n ≥ 15 and even order n ≥ 14, respectively. The values of B(n, 3; 2) when n ≥ 14 are already determined in [1,Theorem 5.1]. Therefore, we have the following result.…”

“…, n − 1} denote the cyclic additive group of order n. Assume B is a subset of Z n , let ∆B := {a − b : where a, b ∈ B and a ̸ = b} ⊂ Z n . In [1], the authors proved following result.…”

“…The necessary conditions for existence of a BSA * (n, {2, 3}; α, ℓ) were given in [1], we summarize them in the following lemma. Lemma 11.…”

“…Research presenting the coding schemes to encode data buses for error correction can be found in [2,8], for low power dissipation [4,9,20,25,28] and for crosstalk avoidance [7,11,22,24,29,30] and for any two of such three criteria [6,13,14,17,18,19,21]. The first memory-less transition bus-encoding technique that covers all three previously described criteria simultaneously; see [1,5] for example. Table 1: Types of worst crosstalk couplings [5].…”

“…In 2021, Ajmal and Zhang [1] provided the complete solution of Lemma 1 and consequently showed that A II,IV (n, 4, 3) = U (n, 3; 2) for each n ≥ 14.…”