New method for high performance multiply-accumulator design

Xia, Bingjie; Liu, Peng; Yao, Qingdong

doi:10.1631/jzus.a0820566

Cited by 12 publications

(10 citation statements)

References 20 publications

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“…Also, it suffers some problems such as, high power dissipation, large number of transistors/area, long delay time, power consumption high. The second common approach is the Pass Transistor Logic (PTL), it is popular as CMOS approach, its features as decreased silicon area, speed, reduced power consumption, slower at reduced power, signi cant power dissipation [25][26][27][28].…”

Section: Low Power Vlsi Approaches Overviewmentioning

confidence: 99%

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

El‐Bendary

El-Badry

2021

Preprint

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Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (7, 4) and (11, 7) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No.Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.

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Section: Low Power Vlsi Approaches Overviewmentioning

confidence: 99%

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

El‐Bendary

El-Badry

2021

Preprint

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“…The MAC proposed by Xia et al (2009) presents 4 bit pipelined split MAC architecture which has been developed for multimedia application supporting multi precision multi-mode operations (Fig. 2c).…”

Section: Shared Segmented Macmentioning

confidence: 99%

“…Fig. 3(a-f): Various logic style for MAC design, (a) SA-FF technique (redrawn) (Matsui et al, 1994), (b) SRPL technique (redrawn) (Parameswar et al, 1996), (c) CMOS technique (Clark et al, 2001;Grossschadl and Kamendje, 2003;Chen et al, 2004;Chang et al, 2009;Xia et al, 2009;Parandeh-Afshar et al, 2010;Hoang et al, 2010;Danysh and Tan, 2005;Quan et al, 2010), (d) CPL (Liao and Roberts, 2002), (e) LVS (Kashfi et al, 2008) and (f) CTGAL redrawn (Wang et al, 2009) J. Applied Sci., 15 (7): 934-946, 2015 Static complementary metal oxide semiconductor: The logic style reported by Clark et al (2001), Grossschadl and Kamendje (2003), Chen et al (2004), Chang et al (2009), Xia et al (2009), Parandeh-Afshar et al (2010), Hoang et al (2010), Danysh and Tan (2005) and Quan et al (2010) is the most common design technique, where each logic network will have pull up and pull down devices, which are controlled by input signals is shown in Fig.…”

Section: Swing Restored Pass Transistor Logicmentioning

confidence: 99%

“…The multiplier scheme in Parameswar et al (1996), Clark et al (2001, Liao and Roberts (2002), Grossschadl and Kamendje (2003), Chen et al (2004), Kashfi et al (2008), Wang et al (2009), Xia et al (2009), Parandeh-Afshar et al (2010, Danysh and Tan (2005) and Quan et al (2010) incorporates Booth radix encoding with Wallace tree or Modified Booth encoding using CSA which reduces the time complexity by N/2 when compared to array structure but…”

Section: Fundamental Components Of Macmentioning

confidence: 99%

“…This MAC architecture is mostly used in Field Programmable Gate Array (FPGA) of Xilinx Corporation and as coprocessor for the LEON2 RISC processor. The shared segmented MAC architecture (Danysh and Tan, 2005;Xia et al, 2009;Parandeh-Afshar et al, 2010;Hoang et al, 2010;Quan et al, 2010) integrates the structures of split parallel unit and recursive characteristics which operate parallel with moderate resources supporting mode-dependent logic. This kind of architecture lacks from throughput limitations owing to compound PPRT.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Survey and Comparative Analysis of Multiply-Accumulate (MAC) Block for Digital Signal Processing Application on ASIC and FPGA

Jebashini¹,

Uma²,

Dhavachelv³

et al. 2015

J. of Applied Sciences

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In the field of semiconductor design industry which, in the contemporary times, has observed exceptional, explosive and exhilarating growth in the development of portable communication devices like mobile phones, IPADS and note books. These real time processing systems perform high computational operations, mainly in the form of butterfly and Multiply Accumulate (MAC). However, these systems are expected to consume high power and are characterized by high data throughput rate. Of the two, MAC is a major component used in portable applications and communication sectors like Wireless Code Division Multiple Access (WCDMA), base station receivers, Successive Interference Canceller (SIC), Orthogonal Frequency Division Multiplexing (OFDM) based wireless devices, channel estimators and carrier synchronizers. In general the MAC block resides in the critical path, which governs the complete power and speed of the system. The efficient utilization of MAC in terms of speed and power depends upon the type of architecture, logic technology style, the fundamental block and primitive cell realization. This study vividly presents the bird eye view on the hitherto work concerning the existing MAC unit in terms of its power performance factors, which helps the future researcher for opting suitable MAC block which can be used in Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) for signal processing applications. The comparative analysis is based on architecture/size, number of clock cycles, Partial Product Reduction Tree (PPRT), functional module, power saving method, logic technology, fabrication process and speed-voltage performance.

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Application of ameliorated Harris Hawks optimizer for designing of low-power signed floating-point MAC architecture

Sarma

Bhargava

Jain

et al. 2021

Neural Comput & Applic

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New method for high performance multiply-accumulator design

Cited by 12 publications

References 20 publications

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

Optimizing of Communications Systems Power Efficiency Considerations: Efficient Implementing Approach of Hamming Codes Utilizing FS-GDI

A Survey and Comparative Analysis of Multiply-Accumulate (MAC) Block for Digital Signal Processing Application on ASIC and FPGA

Application of ameliorated Harris Hawks optimizer for designing of low-power signed floating-point MAC architecture

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