New high radix maximally-redundant signed digit adder

Mekhallalati, M.C.; Ibrahim, M.K.

doi:10.1109/iscas.1999.777914

Cited by 11 publications

(4 citation statements)

References 4 publications

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“…Both of the latter undesirable characteristics may be mitigated through improved encoding and/or adder design. For example, clever designs [19], [20] provide MRSD adders with no hardware redundancy, but the problem of cancellation of leading digits persists.…”

Section: Redundant Representationsmentioning

confidence: 99%

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

Jaberipur

Parhami

Gorgin

2010

IEEE Trans. Comput.

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Abstract-Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a new redundant-digit representation for floating-point numbers that leads to computation speedup in two ways: 1) Reducing the per-operation latency when multiple floating-point additions are performed before result conversion to nonredundant format and 2) Removing the addition associated with rounding. While the first of these advantages is offered by other redundant representations, the second one is unique to our approach, which replaces the power-and area-intensive rounding addition by low-latency insertion of a rounding two-valued digit, or twit, in a position normally assigned to a redundant twit within the redundant-digit format. Instead of conventional sign-magnitude representation, we use a sign-embedded encoding that leads to lower hardware redundancy, and thus, reduced power dissipation. While our intermediate redundant representations remain incompatible with the IEEE 754-2008 standard, many application-specific systems, such as those in DSP and graphics domains, can benefit from our designs. Description of our radix-16 redundant representation and its addition algorithm is followed by the architecture of a floating-point adder based on this representation. Detailed circuit designs are provided for many of the adder's critical subfunctions. Simulation and synthesis based on a 0:13 m CMOS standard process show a latency reduction of 15 percent or better, and both area and power savings of around 58 percent, compared with the best designs reported in the literature.

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Section: Redundant Representationsmentioning

confidence: 99%

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

Jaberipur

Parhami

Gorgin

2010

IEEE Trans. Comput.

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“…Principle of this continuous representation, called Continuous Valued Number System, differs dramatically from digital or multiple valued logic family. In a Multiple Valued Logic (MVL) [1], [2], the number of discrete signal values extends beyond two levels. Therefore, arithmetic systems developed based on the MVL require fewer units, with reduced number of interconnections.…”

Section: Introductionmentioning

confidence: 99%

A mixed-signal adder based on the Continuous Valued Number System

Mirhassani

Kalkat

2008

2008 51st Midwest Symposium on Circuits and Systems

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Continuous Valued Number System (CVNS) representation enables us to integrate complex analog processing functions within digital signal processing units. The CVNS representation is more compatible with analog signals and system, however, it can be applies to applications where traditionally digital arithmetic has been used. The resulted systems usually have compact designs, with reduced number of interconnections, and higher speed of operation. In this paper, design of a mixed signal CVNS adder is proposed, which is used for two operand binary addition. The overall speed of the CVNS adder depends on the analog modular reduction circuits. This paper addresses the limitations in the speed of CVNS adders, and proposes a new method for eliminating this operation from the adder.

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“…There are different approaches available to implement arithmetic architecture with new alternate logic families such as Multiple-Valued-Logic where we increase the signal levels from two values to multiple values 7,8 . Over the last two decades, multiple valued logic circuits and systems have received increasing attention for their potential to reduce interconnect and the number of functional units in VLSI designs.…”

Section: Introductionmentioning

confidence: 99%

16-bit radix-4 continuous valued digit adder

2006

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The Continuous Valued Number System (CVNS) is a novel analog digit number system which employs bit level analog residue arithmetic. The information redundancy among the digits, makes it easy to perform the required binary operations in higher radices, and reduces the implementation area and the number of required interconnections. CVNS theory can open up a new approach for performing digital arithmetic with simple and elementary analog elements, such as current comparators and current mirrors, and with arbitrary precision. In this paper we discuss the design of 16-bit radix-4 CVNS adder with controlled precision, and a two operand binary adder designed, in TSMC CMOS 0.18µm technology, is used to illustrate the techniques.

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New high radix maximally-redundant signed digit adder

Cited by 11 publications

References 4 publications

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

A mixed-signal adder based on the Continuous Valued Number System

16-bit radix-4 continuous valued digit adder

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