New graph-based algorithms for partitioning VLSI circuits

Augeri, Christopher J.; Ali, Hesham H.

doi:10.1109/iscas.2004.1329055

Cited by 10 publications

(4 citation statements)

References 2 publications

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“…Figure 2 states this problem can be considered as a graph partitioning problem where each modules (gates, logic cells, etc.) are taken as vertices (nodes or points) and the connection between two logic cells represents the edges [6]. The algorithm starts with gates placed on the graph as vertex, and an initial population has to be chosen as the different permutations of various vertices of the given graph.…”

Section: Graphical Representation Of Physical Design Componentsmentioning

confidence: 99%

Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Shanavas

Gnanamurthy²

2014

Mathematical Problems in Engineering

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In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

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Section: Graphical Representation Of Physical Design Componentsmentioning

confidence: 99%

Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Shanavas

Gnanamurthy²

2014

Mathematical Problems in Engineering

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“…The problem can be viewed as a graph partitioning problem where each modules (gates etc.) are taken as vertices and the connection between them represents the edges between the nodes [12], [13].…”

Section: Partitioningmentioning

confidence: 99%

Physical Design Optimization Using Evolutionary Algorithms

Shanavas¹,

Gnanamurthy²

2012

IJCEE

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Abstract-Minimizing the wirelength plays an important role in physical design automation of very large scale integration(VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay have prime importance. In VLSI circuit floorplanning the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning has influence on other criteria like power, cost, clock speed etc. Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning.MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

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“…The problem can be viewed as a graph partitioning problem where each module (gates etc.) is taken as vertices and the connection between them represents the edges between the nodes [12,13].…”

Section: Partitioningmentioning

confidence: 99%

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

Shanavas¹,

Gnanamurthy

2011

VLSI Design

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Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.

show abstract

New graph-based algorithms for partitioning VLSI circuits

Cited by 10 publications

References 2 publications

Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Physical Design Optimization Using Evolutionary Algorithms

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

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