New Current Mode Wheatstone Bridge Topologies with Intrinsic Linearity

Safari, Leila; Barile, Gianluca; Stornelli, Vincenzo; Ferri, Giuseppe; Leoni, Alfiero

doi:10.1109/prime.2018.8430363

Cited by 20 publications

(15 citation statements)

References 12 publications

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“…The proposed readout circuit of Figure 3 has been simulated using Spice in 0.35 μm CMOS technology and a supply voltage of ±1.65 V. For the required VCIIs, the circuit of [27] (Figure 4a) has been used with the same aspect ratios and biasing. Current sources have been implemented by means of simple current mirrors.…”

Section: Simulation Results and Measurementsmentioning

confidence: 99%

“…While its introduction is dated back to 2001 [23,24], it is recently gaining more attention [24,25,26]. VCII has been profitably used in fields like current-mode Wheatstone bridges [27], active filters [28], and interfaces for silicon photomultipliers [29,31]. It is characterized by a current buffer between Y and X terminals (having named β the ratio between I x and I y ) and a voltage buffer between X and Z terminals (having named α the ratio between V z and V x ) .…”

Section: The Proposed Interfacementioning

confidence: 99%

“…The VCII used in the simulations: ( a ) Topology (see [27]), ( b ) AC performances (determined with a 3 pF load at X), ( c ) DC performances (determined with a 1 kΩ load at Y for β simulations, and with a 100 kΩ load at Z for α simulations).…”

Section: Figurementioning

confidence: 99%

“…In this paper, we describe and prototype a novel current mode interface based, for the first time, on the second-generation voltage conveyor, a three terminal active block that, differently from Op-Amps or second-generation current conveyors (CCIIs), allows for both current domain and voltage domain signal processing without adding extra components or losing performances [23,24,25,26,27,28,29,30]. The interface fulfils many important features namely: Very simple implementation and insensitivity to large sensor parasitic capacitances thanks to an active compensation of the current taken from them.…”

Section: Introductionmentioning

confidence: 99%

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A VCII-Based Stray Insensitive Analog Interface for Differential Capacitance Sensors

Barile

Safari

Ferri

et al. 2019

Sensors

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In this paper, a novel approach to implement a stray insensitive CMOS interface for differential capacitive sensors is presented. The proposed circuit employs, for the first time, second-generation voltage conveyors (VCIIs) and produces an output voltage proportional to differential capacitor changes. Using VCIIs as active devices inherently allows the circuit to process the signal in the current domain, and hence, to benefit from its intrinsic advantages, such as high speed and simple implementation, while still being able to natively interface with voltage mode signal processing stages at necessity. The insensitiveness to the effects of parasitic capacitances is achieved through a simple feedback loop. In addition, the proposed circuit shows a very simple and switch-free structure (which can be used for both linear and hyperbolic sensors), improving its accuracy. The readout circuit was designed in a standard 0.35 μm CMOS technology under a supply voltage of ±1.65 V. Before the integrated circuit fabrication, to produce tangible proof of the effectiveness of the proposed architecture, a discrete version of the circuit was also prototyped using AD844 and LF411 to implement a discrete VCII. The achieved measurement results are in good agreement with theory and simulations, showing a constant sensitivity up to 412 mV/pF, a maximum linearity error of 1.9%FS, and acknowledging a good behavior with low baseline capacitive sensors (10 pF in the proposed measurements). A final table is also given to summarize the key specs of the proposed work comparing them to the available literature.

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Section: Simulation Results and Measurementsmentioning

confidence: 99%

Section: The Proposed Interfacementioning

confidence: 99%

Section: Figurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A VCII-Based Stray Insensitive Analog Interface for Differential Capacitance Sensors

Barile

Safari

Ferri

et al. 2019

Sensors

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“…The potential effect of parasitic stray capacitance is not targeted within this work. Refer to [17,18] for further details on compensating non-linearity and parasitic parameters in resistive and capacitive sensor bridges.…”

Section: Main Measurement Resultsmentioning

confidence: 99%

A Fully-Differential Switched-Capacitor Dual-Slope Capacitance-To-Digital Converter (CDC) for a Capacitive Pressure Sensor

Rogi

Buffa

Milleri

et al. 2019

Sensors

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This article focuses on a proposed Switched-Capacitor Dual-Slope based CDC. Special attention is paid to the measurement setup using a real pressure sensor. Performance scaling potential as well as dead zones are pointed out and discussed. In depth knowledge of the physical sensor behavior is key to design an optimal readout circuit. While this is true for high-end applications, low-performance IoT (Internet of Things) sensors aim at moderate resolution with very low power consumption. This article also provides insights into basic MEMS (Micro-Electro-Mechanical-System) physics. Based on that, an ambient air pressure sensor model for SPICE (Simulation-Program-with-Integrated-Circuit-Emphasis) circuit simulators is presented. The converter concept was proven on silicon in a 0.13 μ m process using both a real pressure sensor and an on-chip dummy MEMS bridge. A 3.2-ms measurement results in 13-bit resolution while consuming 35 μ A from a 1.5-V supply occupying 0.148 mm2. A state-of-the-art comparison identifies potential room for improvements towards hybrid solutions, which is proposed in subsequent publications already.

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A second‐generation voltage conveyor (VCII)–based simulated grounded inductor

Safari

Yüce

Mınaeı

et al. 2020

Circuit Theory & Apps

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SummaryIn this paper, an implementation of a simulated grounded inductor (SGI) based on a recently developed active building block called second‐generation voltage conveyor (VCII) is proposed. The proposed SGI employs two VCIIs, two resistors, and one grounded capacitor, which is preferred when integration is involved. More importantly, unlike most of the other previously reported SGIs, this one is free from any restrictive matching conditions. A complete analysis of nonidealities along with sensitivity treatment by considering parasitic impedances and nonideal gains of the VCII are performed. A simple VCII circuit is designed to be used in the implementation of the proposed SGI. To support the presented theory, Pspice simulation results using 0.18‐μm CMOS technology parameters and supply voltage of ±0.9 V are provided. On the basis of the achieved results, the proposed SGI operates in a good agreement with an ideal inductor. The power consumption is only 0.65 mW, and the parasitic series impedance is approximately 191.9 Ω. The applicability of the proposed SGI is tested by using it in a standard second‐order high‐pass RLC filter.

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New Current Mode Wheatstone Bridge Topologies with Intrinsic Linearity

Cited by 20 publications

References 12 publications

A VCII-Based Stray Insensitive Analog Interface for Differential Capacitance Sensors

A VCII-Based Stray Insensitive Analog Interface for Differential Capacitance Sensors

A Fully-Differential Switched-Capacitor Dual-Slope Capacitance-To-Digital Converter (CDC) for a Capacitive Pressure Sensor

A second‐generation voltage conveyor (VCII)–based simulated grounded inductor

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