New Cost-Effective VLSI Implementation of a 2-D Discrete Cosine Transform and Its Inverse

Gong, Danian; He, Yun; Cao, Zhigang

doi:10.1109/tcsvt.2004.825575

Cited by 49 publications

(17 citation statements)

References 19 publications

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“…The parallel-pipeline architecture and arithmetic units operating at half the frequency gives an input data rate of 300 MHz, far higher than that of the fastest processor listed in this table [11]. This speed does not imply any additional cost in terms of the number of gates since it is similar to that of the other designs proposed which offer an efficient hardware complexity [5,6,8,9,13,20].…”

Section: Implementation and Comparisonsmentioning

confidence: 85%

“…As compared with the existing design listed in Table 3, the proposed processor is clearly superior in terms of speed even for those processors that use a better technology [11,15]. The parallel-pipeline architecture and arithmetic units operating at half the frequency gives an input data rate of 300 MHz, far higher than that of the fastest processor listed in this table [11].…”

Section: Implementation and Comparisonsmentioning

confidence: 88%

“…In the literature, there are many VLSI implementations proposed for DCT and its inverse (IDCT) which, to a greater or lesser extent, search for some of the following characteristics: lowcost area [4][5][6][7][8][9], regularity to reduce the design effort [10,11], high throughput [4,5,9,[11][12][13] and low power [4,14,15]. Different approaches have been proposed to implement the 2-D DCT/IDCT: rowcolumn decomposition method, the direct method and other minority alternatives based on transforms (as DFT [16] and DHT [17]), CORDIC algorithms [18] and systolic array implementations [19].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip

Ruiz

Michell

Burón

2006

J VLSI Sign Process Syst Sign Image Video Technol

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Abstract. This paper presents a 2-D DCT/IDCT processor chip for high data rate image processing and video coding. It uses a fully pipelined row-column decomposition method based on two 1-D DCT processors and a transpose buffer based on D-type flip-flops with a double serial input/output data-flow. The proposed architecture allows the main processing elements and arithmetic units to operate in parallel at half the frequency of the data input rate. The main characteristics are: high throughput, parallel processing, reduced internal storage, and maximum efficiency in computational elements. The processor has been implemented using standard cell design methodology in 0.35 mm CMOS technology. It measures 6.25 mm 2 (the core is 3 mm 2 ) and contains a total of 11.7 k gates. The maximum frequency is 300 MHz with a latency of 172 cycles for 2-D DCT and 178 cycles for 2-D IDCT. The computing time of a block is close to 580 ns. It has been designed to meets the demands of IEEE Std. 1,180-1,990 used in different video codecs. The good performance in the computing speed and hardware cost indicate that this processor is suitable for HDTV applications.

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Section: Implementation and Comparisonsmentioning

confidence: 85%

Section: Implementation and Comparisonsmentioning

confidence: 88%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip

Ruiz

Michell

Burón

2006

J VLSI Sign Process Syst Sign Image Video Technol

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“…Table II lists features of the proposed processor and other DCT implementations selected from among those which fulfill the specifications of the standard [2]. The parallel-pipeline architecture and arithmetic units operating at half the frequency gives an input data rate of 300MHz, far higher than that of the fastest processor listed in this table [3] [7]. This speed does not imply any additional cost in terms of the number of gates since it offers an efficient hardware implementation.…”

Section: Implementation and Comparisonsmentioning

confidence: 99%

“…Thus, the DCT has been applied for most of recent picture international standards as JPEG, MPEG, H.261 and H.263, as well as in high-definition television (HDTV) systems. The computation complexity requirements in many real-time applications often lead to the use of efficient dedicated hardware (ASIC's) operating at high speed with an acceptable cost in area [3]- [7]. This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with a high input data rate and a cost-effective hardware.…”

Section: Introductionmentioning

confidence: 99%

High throughput 2D DCT/IDCT processor for video coding

Ruiz

Michell

Burón

2005

IEEE International Conference on Image Processing 2005

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This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the processing elements and arithmetic units to work in parallel at half the frequency of the data input rate. A fully pipelined row-column decomposition method based on two 1-D DCTs and a transpose buffer based on D-type flip-flops are used. The processor has been implemented in a 0.35-µm CMOS process with a core area of 3mm 2 and 11.7k gates. It meets the requirements of IEEE Std. . The data input rate frequency is 300MHz with a latency of 172 cycles for 2-D DCT and 178 cycles for 2-D IDCT. The proposed design is compact and suitable for HDTV applications.

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