New Block Cipher: ARIA

Kwon, Daesung; Kim, Jae-Sung; Park, Sangwoo; Sung, Soo Hak; Sohn, Yaekwon; Song, Jung Hwan; Yeom, Yongjin; Yoon, E-Joong; Lee, Sang-Jin; Lee, Jaewon; Chee, Seongtaek; Han, Daewan; Hong, Jin

doi:10.1007/978-3-540-24691-6_32

Cited by 112 publications

(88 citation statements)

References 7 publications

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“…The larger basic block size has an advantage in that more random schedules are generated, which increases the chances of generating optimal result. We measured the reduction in power consumption between existing algorithms and the proposed algorithm using benchmark programs such as qsort (quick sort), fft (fast Fourier transform), ARIA (encryption algorithm) [19], JPEG (image compression algorithm), mat inv (matrix inversion) and edge detect (edge detection algorithm).…”

Section: Resultsmentioning

confidence: 99%

A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems

Lee¹,

Lee

Hwang

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents an efficient instruction scheduling algorithm which generates low-power codes for embedded system applications. Reordering and recoding are concurrently applied for low-power code generation in the proposed algorithm. By appropriate reordering of instruction sequences, the efficiency of instruction recoding is increased. The proposed algorithm constructs program codes on a basic-block basis by selecting a code sequence from among the schedules generated randomly and maintained by the system. By generating random schedules for each of the basic blocks constituting an application program, the proposed algorithm constructs a histogram graph for each of the instruction fields to estimate the figure-of-merits achievable by reordering instruction sequences. For further optimization, the system performs simulated annealing on the generated code. Experimental results for benchmark programs show that the codes generated by the proposed algorithm consume 37.2% less power on average when compared to the previous algorithm which performs list scheduling prior to instruction recoding.

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Section: Resultsmentioning

confidence: 99%

A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems

Lee¹,

Lee

Hwang

2010

IEICE Trans. Inf. & Syst.

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“…By using (BCwC) q,m type (where q = 3, m = 4 or q = 4, m = 3), 12 × 12 binary matrices with the maximum branch number 8, which form, at the same time, the extended binary Golay codes ([24, 12, 8]), are generated, 5. Using the proposed methods, we generate 16×16 involutory (and orthogonal) and noninvolutory binary matrices with the maximum branch number 8, and also give two selected examples with implementation properties better than the one in ARIA block cipher [11] (especially on 32-bit platforms), 6. We apply (BHwC) t,m type (where t = 2 and m = 8) to generate 32×32 binary matrices with the maximum achievable branch number 12 and Hamming weight 11 in each row and column, and give some examples of binary matrices with good implementation properties (especially on 8-bit platforms).…”

Section: Our Contributionsmentioning

confidence: 99%

Efficient methods to generate cryptographically significant binary diffusion layers

Akleylek¹,

Rijmen

Sakallı

et al. 2017

IET Information Security

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In this paper, we propose new methods using a divide-and-conquer strategy to generate n × n binary matrices (for composite n) with a high/maximum branch number and the same Hamming weight in each row and column. We introduce new types of binary matrices, namely (BHwC) t,m and (BCwC) q,m types, which are a combination of Hadamard and circulant matrices, and the recursive use of circulant matrices, respectively. With the help of these hybrid structures, the search space to generate a binary matrix with a high/maximum branch number is drastically reduced.By using the proposed methods, we focus on generating 12 × 12, 16 × 16 and 32 × 32 binary matrices with a maximum or maximum achievable branch number and the lowest implementation costs (to the best of our knowledge) to be used in block ciphers. Then, we discuss the implementation properties of binary matrices generated and present experimental results for binary matrices in these sizes. Finally, we apply the proposed methods to larger sizes, i.e., 48 × 48, 64 × 64 and 80 × 80 binary matrices having some applications in secure multi-party computation and fully homomorphic encryption.

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“…Then we set [3] Here, and are odd and even round functions. The 128-bit keys (i=1, 2, 3, 4) of round functions are fixed to be the rational part of .…”

Section: B Key Schedulementioning

confidence: 99%

“…ARIA [3] has a structure similar to AES (Advanced Encryption Standard): it is designed by Korean scientists and is a 128-bit substitution-permutation network block cipher. Each round of the cipher consists of three parts, round key addition (RKA), substitution layer (SL) and diffusion layer (DL).…”

Section: Introductionmentioning

confidence: 99%

Revised Unified Impossible Differential Cryptanalysis of ARIA

Zhong¹,

Xue²,

Mu³

et al. 2015

Proceedings of the 2015 International Conference on Electronic Science and Automation Control

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Abstract-Unified Impossible Differential (UID) cryptanalysis is a systematic method to find impossible differentials for block ciphers and there are large amount of cryptanalysis results coming out by using it. ARIA is a Korean block cipher expecting no impossible differential chains on four or more rounds. In this paper, we apply UID to ARIA and 89136 four rounds impossible differential chains are found. With the optimization of the conflict searching algorithms, UID gets better results compared with former cryptanalysis results. Moreover, we conclude that no impossible differential chains with number of rounds larger than four can be found by the UID method.

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New Block Cipher: ARIA

Cited by 112 publications

References 7 publications

A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems

A Concurrent Instruction Scheduling and Recoding Algorithm for Power Minimization in Embedded Systems

Efficient methods to generate cryptographically significant binary diffusion layers

Revised Unified Impossible Differential Cryptanalysis of ARIA

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