New ATPG techniques for logic optimization

Jacoby, R.; Moceyunas, P.; Cho, H.; Hachtel, Gary D.

doi:10.1109/iccad.1989.77010

Cited by 16 publications

(4 citation statements)

References 13 publications

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“…The table visited is used to store the visited subtree so the procedure avoids revisiting identical subproblems. This technique has been widely used in some other related verification problems [11,12] and can be easily applied to XBDDs. The visited subtree checking can be done by one pointer comparison.…”

Section: Combinational Verificationmentioning

confidence: 98%

Extended BDDs: Trading of canonicity for structure in verification algorithms

Plessier

Hachtel

Somenzi

1994

Form Method Syst Des

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Abstract. We present an extension to binary decision diagrams (BDDs) that exploits the information contained in the structure of a given circuit to produce a compact, semicanonical, representation.The resulting XBDDs (extended BDDs) retain many of the advantages of BDDs, while at the same time allowing one to deal with larger circuits.We propose algorithms for verification of combinational circuits based on XBDDs that overcome the exponential growth in the number of nodes in the BDDs for some specific circuits such as the multipliers. While the approach remains cpu-time intensive, we believe it is the first to "exactly" verify the most difficult (median) output of a 16-bit multiplier. Experimental results are presented to support our claim that the XBDD approach is the "best" for multiplier verification.

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Section: Combinational Verificationmentioning

confidence: 98%

Extended BDDs: Trading of canonicity for structure in verification algorithms

Plessier

Hachtel

Somenzi

1994

Form Method Syst Des

Self Cite

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“…More implications are found than in previous algorithms (such as [29,14]), and the search space is reduced enough that TEGUS only computes global implications statically before the branch-and-bound search is started, not dynamically at every branch point of the search. Some benefits of dynamically computing an incomplete set of global implications [29,30,16,31,32,17] are a result of this ordering dependence. For extremely difficult redundant faults, the iterated computation can also be applied dynamically during the search (although this is not necessary for any faults in the ISCAS networks).…”

Section: Iterated Global Implicationsmentioning

confidence: 99%

“…The uniformity of the SAT representation is an advantage for computing global implications. Structural algorithms [34,29,30,31,32,33] have to handle special cases for implications in forward versus backward directions, for implications of different gate types, for implications in both the good and faulty network, and for implications involving the fault propagation path. Having to check all these special cases can degrade overall performance, and is complicated enough that often global implications are not computed at all (e.g., [36,37,35,38]) even though they are known to significantly improve robustness.…”

Section: Iterated Global Implicationsmentioning

confidence: 99%

Combinational test generation using satisfiability

Stephan

Brayton

Sangiovanni-Vincentelli

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

246

165

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We present a robust and efficient algorithm for combinational test generation using a reduction to satisfiability (SAT). The algorithm, TEGUS, has the following features. We choose a form for the test set characteristic equation which minimizes its size. The simplified equation is solved by an algorithm for SAT using simple, but powerful, greedy heuristics, ordering the variables using depth-first search and selecting a variable from the next unsatisfied clause at each branching point. For difficult faults the computation of global implications is iterated, which finds more implications than previous approaches and subsumes structural heuristics such as unique sensitization. Without random tests or fault simulation, TEGUS completes on every fault in the ISCAS networks, demonstrating its robustness, and is 11 times faster for those networks which have been completed by previous algorithms. Our publicly available implementation of TEGUS can be used as a base line for comparing test generation algorithms; we present comparisons with 45 recently published algorithms. TEGUS combines the advantages of the elegant organization of SAT-based algorithms, such as that by Svanaes, with the efficiency of structural algorithms, such as the D-algorithm.

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“…In the first phase, a combinational test that propagates the fault effects to either the primary outputs or the next state variables is generated using a state-of-the-art ATPG algorithm [14], extended to 'This work was supported in part by NSFfDARPA grant MIP-…”

Section: Test Generation Proper Is Divided In Three Steps (As In [12]mentioning

confidence: 99%

Fast Sequential ATPG Based on Implicit State Enumeration

Cho¹,

Hachtel²,

Somenzi³

1991, Proceedings. International Test Conference

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The knowledge of the State Transition Graph (STG) of a sequential circuit helps in generating test sequences. For instance, by determining that a set of states is not reachable from the reset state, it is possible to identify a certain type of sequentially untestable faults. However, until recently, the ability of algorithms to store the STG of a sequential circuit has been limited to small instances. Recent advances in sequential circuit verification, based on the use of binary decision diagrams and new powerful implicit enumeration algorithms, have dramatically improved our ability to deal with large numbers of states. In this paper we report on the application of these algorithms to the problems of generating justification sequences, identifying redundancies, and dealing with hard-to-detect faults. Our experiments show substantial improvements over previously published results.

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New ATPG techniques for logic optimization

Cited by 16 publications

References 13 publications

Extended BDDs: Trading of canonicity for structure in verification algorithms

Extended BDDs: Trading of canonicity for structure in verification algorithms

Combinational test generation using satisfiability

Fast Sequential ATPG Based on Implicit State Enumeration

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