New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns

Abstract

This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach

Application of New Approach of design flow for Hardware/Software Embedded System with the Use of Design Patterns in Fuzzy control system

“…From this level, the implementation step is achieved in order to generate the RTL architecture. Our approach of design try to solve the complexity problem, it consists to develop two intermediate environments in order to minimize the gap between application development and architecture synthesis [10,11,12,20,21,22].…”

“…Many researches are performed for the reusability problem in order to develop new design tools that encapsulate all codesign phases in order to implement intellectual property (IP) blocks [20]. One attempt proposed in [21,22] have as aim to develop the smartcell design tools in order to implement HW and SW IP blocks for heterogeneous platforms. Our contribution to resolve the reusability problem consists in the synthesis of IP blocks for hardware and software solutions from direct acyclic graph (DAC).…”

APPLIED HW/SW CO-DESIGN: Using the Kendall Tau Algorithm for Adaptive Pacing

“…Another advantage of this approach is that custom hardware can exploit an algorithm's inherent parallelism by executing multiple independent data sets on similar copies of hardware at a time. [9] In the biomedical industry, In contrast, a FPGA can be re-routed without an expensive mask and etch process, thus bypassing the main problem with ASICs. Accordingly, this thesis studies hardware implemented on an FPGA with the notion that all hardware models can be later synthesized as an ASIC.…”