NeuronFlow: A Hybrid Neuromorphic – Dataflow Processor Architecture for AI Workloads

Moreira, Orlando; Yousefzadeh, Amirreza; Chersi, Fabian; Kapoor, Ajay; Zwartenkot, Rik-Jan; Pan, Qiao; Cinserin, G.; Khoei, Mina A.; Lindwer, Menno; Tapson, Jonathan

doi:10.1109/aicas48895.2020.9073999

Cited by 17 publications

(13 citation statements)

References 11 publications

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“…Send ∆X j (t) to successors end if end for GrAIMattersLab [15,16] implemented this algorithm in the NeuronFlow processor architecture [15,16].…”

Section: Deltanetworkmentioning

confidence: 99%

Neural Network Optimization for Reinforcement Learning Tasks Using Sparse Computations

Ivanov¹,

Киселев²,

Larionov³

2022

Preprint

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This article proposes a sparse computation-based method for optimizing neural networks for reinforcement learning (RL) tasks. This method combines two ideas: neural network pruning and taking into account input data correlations; it makes it possible to update neuron states only when changes in them exceed a certain threshold. It significantly reduces the number of multiplications when running neural networks. We tested different RL tasks and achieved 20-150x reduction in the number of multiplications. There were no substantial performance losses; sometimes the performance even improved.

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“…Send ∆X j (t) to successors end if end for GrAIMattersLab [15,16] implemented this algorithm in the NeuronFlow processor architecture [15,16].…”

Section: Deltanetworkmentioning

confidence: 99%

Neural Network Optimization for Reinforcement Learning Tasks Using Sparse Computations

Ivanov¹,

Киселев²,

Larionov³

2022

Preprint

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“…Moving on to hardware platforms, most existing work in neuromorphic hardware has been the production of prefabricated ASICs in both the commercial sector with chips like Intel's Loihi [14], IBM's TrueNorth [13], the Akida Neuromorphic SoC [38], or Qualcomm Zeroth [39] and the academic environment with chips like SpiNNaker [40], DYNAPs [41], NeuronFlow [42], SpinalFlow [43], or ODIN [44]. Of these, ODIN is notable in that it has an open source verilog implementation despite not being targeted towards FPGAs.…”

Section: Scalability Analysismentioning

confidence: 99%

RANC: Reconfigurable Architecture for Neuromorphic Computing

Mack

Purdy

Rockowitz

et al. 2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Neuromorphic architectures have been introduced as platforms for energy efficient spiking neural network execution. The massive parallelism offered by these architectures has also triggered interest from nonmachine learning application domains. In order to lift the barriers to entry for hardware designers and application developers we present RANC: a Reconfigurable Architecture for Neuromorphic Computing, an opensource highly flexible ecosystem that enables rapid experimentation with neuromorphic architectures in both software via C++ simulation and hardware via FPGA emulation. We present the utility of the RANC ecosystem by showing its ability to recreate behavior of the IBM's TrueNorth and validate with direct comparison to IBM's Compass simulation environment and published literature. RANC allows optimizing architectures based on application insights as well as prototyping future neuromorphic architectures that can support new classes of applications entirely. We demonstrate the highly parameterized and configurable nature of RANC by studying the impact of architectural changes on improving application mapping efficiency with quantitative analysis based on Alveo U250 FPGA. We present post routing resource usage and throughput analysis across implementations of Synthetic Aperture Radar classification and Vector Matrix Multiplication applications, and demonstrate a neuromorphic architecture that scales to emulating 259K distinct neurons and 73.3M distinct synapses.

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“…Before Loihi, the SpiNNaker Project [4] used a very large array of custom chips to evaluate spiking neural networks. GrAI Matter Lab's NeuronFlow [14] combines a spiking neuron model and a dataflow design methodology in the design of GML's first chip: GrAIOne [15]. Their architecture allows for low latency and low power execution of dataflow graphs and spiking neural networks using a many-core grid of neuron cores that communicate using events.…”

Section: Related Workmentioning

confidence: 99%

How to exploit sparsity in RNNs on event-driven architectures

Brils

Waeijen²,

Pourtaherian³

2021

Proceedings of the 24th International Workshop on Software and Compilers for Embedded Systems

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Event-driven architectures have been shown to provide low-power, low-latency artificial neural network (ANN) inference. This is especially beneficial on Edge devices, particularly when combined with sparse execution. Recurrent neural networks (RNNs) are ANNs that emulate memory. Their recurrent connection enables the reuse of previous output for the generation of new output. However, when trying to use RNNs in a sparse context on event-driven architectures, novel challenges in synchronization and the usage of sparse data are encountered. In this work, these challenges are systematically analyzed, and mechanisms to overcome them are proposed. Experimental results of a monocular depth estimation use case on the NeuronFlow architecture show that sparsity in RNNs can be exploited effectively on event-driven architectures. CCS CONCEPTS• Hardware → Asynchronous circuits; • Computer systems organization → Embedded hardware; Embedded software; Neural networks.

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NeuronFlow: A Hybrid Neuromorphic – Dataflow Processor Architecture for AI Workloads

Cited by 17 publications

References 11 publications

Neural Network Optimization for Reinforcement Learning Tasks Using Sparse Computations

Neural Network Optimization for Reinforcement Learning Tasks Using Sparse Computations

RANC: Reconfigurable Architecture for Neuromorphic Computing

How to exploit sparsity in RNNs on event-driven architectures

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