Neuron Array With Plastic Synapses and Programmable Dendrites

Abstract

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing

“…Analog or digital signals can be routed on the same fabric [1] and can be used by CABs or CLBs. Early attempts at these approaches were considered earlier [36,37]. Why would one take this approach?…”

“…Over a decade of consistent FPAA development and application design has roughly converged on a typical mixture of several medium level components per CAB (Transconductance Amplifiers (OTAs), FG OTAs, T-gates), along with a few low level elements (transistors, FG transistors, capacitors). A few CABs might be specialized for larger functions (e.g., signal-by-signal multipliers [1], sensor interfacing [45], neurons [36]), showing their relative importance in these discussions. Most of these elements have at least one FG parameter that is part of the particular device used.…”

Programmable and Configurable Analog Neuromorphic ICs

“…Figure 10.6a shows a general block-diagram of the analog computing array, with comparison to traditional digital computation. Recent results show greater improvement in power efficiency based on neural-inspired approaches enabling wordspotting computation through a dendritic-rich neuron network (George and Hasler 2011; Ramakrishnan et al 2012). Performing the computation in the memory cells themselves avoids the throughput bottlenecks found in most signal processing systems.…”

Spatio-temporal Spike Pattern Classification in Neuromorphic Systems

“…Multi-compartmental models, conductance-based neurons [26], short-term synaptic plasticity, and dendritic computation [27,28,29,30,31] are all examples of strategies that allow such properties.…”

“…For example Wang and Liu [28] demonstrate a VLSI neuron chip with programmable dendritic compartments and delay elements, showing how different spatio-temporal input patterns have different effects on the evoked dendritic integration. Analogous approaches have been proposed using floating-gate structures [30,52]. But simpler Integrate and Fire (IF) neuron circuits can also implement delay elements without having to implement complex dendritic spatial structures.…”