Neural Network Based Silent Error Detector

Wang, Chen; Dryden, Nikoli; Cappello, Franck; Snir, Marc

doi:10.1109/cluster.2018.00035

Cited by 10 publications

(3 citation statements)

References 29 publications

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“…Yang N et al proposed a method called Program Vulnerable Instructions Identification (PVInsiden) to identify program vulnerable instructions that were likely to cause SDCs [9]. Wang C et al proposed a neural network detector which could find out the SDC errors [10] iterated many times in the program.…”

Section: Related Workmentioning

confidence: 99%

“…Definition 4: The instruction can be expressed as a six-tuple as shown in the equation (10). O S (O d ) is the source(destination) operand in the instruction I .…”

Section: A Dependency Instruction Features Extractionmentioning

confidence: 99%

“…Recently, literature focus on analyze vulnerable parts of the program and selectively reinforce them, including SDC vulnerability analysis based on fault injection [6], based on program static analysis [7] and machine learning-based SDC vulnerability analysis [8]. The fault injection methods injected the needed instruction information of faults into the schedule sequentially, which were often costly [6], [9], [10]. Detection methods based on static analysis analyzed features of instructions and the SDC vulnerability of programs without fault injections, but the time cost increased exponentially as the size of the program raised [11], [12].…”

Section: Introductionmentioning

confidence: 99%

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Vulnerability Analysis of Instructions for SDC-Causing Error Detection

Zheng

Zhuang

et al. 2019

IEEE Access

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Due to the centralization of communication in the management of data generated by diverse Internet of Thing (IoT) devices, there is a lack of reliability when data is being transferred and stored. Among errors caused by various behaviors, Silent Data Corruption (SDC) error, owing to stealthy destruction without error prompt, is one of the most difficult data consistency problems in the storage system, whether it is a traditional multi-control, distributed storage, or public cloud storage. Nowadays, for SDC error detection, extracting instruction features to analyze vulnerabilities of programs or instructions has still not been fully explored. Literature generally just count the number of possible features, without mining the inter-characteristic of the instruction and correlation between them. Thus, we propose a method of SDC-causing Error Detection based on Support Vector Regression (SED-SVR) for fully exploiting the correlation between data features. Specifically, firstly, we extract instruction features based on the SDC vulnerability of program instructions by analyzing results of fault injections. Secondly, we establish the instruction SDC vulnerability prediction model based on SVR and propose our SED-SVR model. Thirdly, according to the predicted values of SDC vulnerability, we develop some solutions for faults tolerance of target programs by different granularity of instruction redundancy. The experimental results show that our SED-SVR has higher fault detection rate with lower performance overhead.

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Section: Related Workmentioning

confidence: 99%

“…Definition 4: The instruction can be expressed as a six-tuple as shown in the equation (10). O S (O d ) is the source(destination) operand in the instruction I .…”

Section: A Dependency Instruction Features Extractionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Vulnerability Analysis of Instructions for SDC-Causing Error Detection

Zheng

Zhuang

et al. 2019

IEEE Access

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SDC Error Detection by Exploring the Importance of Instruction Features

Fang

Yan

et al. 2021

Wireless Algorithms, Systems, and Applications

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Response of HPC hardware to neutron radiation at the dawn of exascale

et al. 2023

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Every computation presents a small chance that an unexpected phenomenon ruins or modifies its output. Computers are prone to errors that, although may be very unlikely, are hard, expensive or simply impossible to avoid. In the exascale, with thousands of processors involved in a single computation, those errors are especially harmful because they can corrupt or distort the results, wasting human and material resources. In the present work, we study the effect of ionizing radiation on several pieces of commercial hardware, very common in modern supercomputers. Aiming to reproduce the natural radiation that could arise, CPUs (Xeon, EPYC) and GPUs (A100, V100, T4) are subject to a known flux of neutrons coming from two radioactive sources, namely $$^{252}$$ 252 Cf and $$^{241}$$ 241 Am-Be, in a special irradiation facility. The working hardware is irradiated under supervision to quantify any appearing error. Once the hardware response is characterised, we are able to scale down the radiation intensity and to estimate the effects on standard data centres. This can help administrators and researchers to develop their contingency plans and protocols.

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Neural Network Based Silent Error Detector

Cited by 10 publications

References 29 publications

Vulnerability Analysis of Instructions for SDC-Causing Error Detection

Vulnerability Analysis of Instructions for SDC-Causing Error Detection

SDC Error Detection by Exploring the Importance of Instruction Features

Response of HPC hardware to neutron radiation at the dawn of exascale

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