Neural Models and Algorithms for Digital Testing

Chakradhar, Srimat; Agrawal, Vishwani D.; Bushnell, M.L.

doi:10.1007/978-1-4615-3958-2

Cited by 42 publications

(33 citation statements)

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“…This expression has the same form as the energy function of a neural network. We recently presented energy minimization solutions of the test generation problem [13]. By combining these results, in the future, it may become possible to establish equivalence between direct-search (e.g., D-algorithm, Podem), energy minimization (including simulated annealing), and logic transformation (as presented in this paper) methods.…”

Section: Resultsmentioning

confidence: 94%

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A novel VLSI solution to a difficult graph problem

Chakradhar

Agrawal²

1991

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

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In this paper, we present a VLSI solution of the independent set problem. This graph problem occurs in many applications including computer-aided design. Our solution is based on a novel transformation of the graph to a logic circuit. The vertices in the graph are encoded with Boolean variables whose relationships are represented in the logic circuit. The transformation is derived from the energy relation of the neural network model of the logic circuit. Each input vector provides one solution of the independent set problem. The independent set consists of only vertices with true encoding. This new methodology has the potential of solving the problem in real time if programmable logic is used.

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Section: Resultsmentioning

confidence: 94%

“…Model for a Boolean Gate: The energy function for an AND gate with input signals 2 1 and 2 2 , and output signal 2 3 is given by [13]: N D ( 2 3 7 2 1 , 2 and 23 can assume only binary values. All operations are arithmetic and not Boolean.…”

Section: Conflict Graphs Of Boolean Gatesmentioning

confidence: 99%

A novel VLSI solution to a difficult graph problem

Chakradhar

Agrawal²

1991

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

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“…The term combinational circuits is used for circuits with only Boolean logic gates. Methods using energy minimization [9], [10], Boolean satisfiability [11], and binary decision diagrams [12], [13] have been recently proposed for generating tests for large combinational circuits. These methods are fast and practical, and share the following similarities: 1) they represent logic values on signals by Boolean variables, 2) they construct energy functions or satisfiability expressions using these Boolean variables, and 3) they solve the energy minimization or the satisfiability problem to obtain a set of Boolean values for the variables, and this set corresponds to a test for the fault.…”

Section: Introductionmentioning

confidence: 99%

Redundancy removal and test generation for circuits with non-Boolean primitives

Chakradhar¹,

Rotherweiler²,

Agrawal³

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Production VLSI circuits typically consist of primitives like tristate buffers, bidirectional buffers, and bus configurations that assume non-Boolean values like the high-impedance state. We describe a systematic methodology for extending test generation algorithms that work on combinational circuits with only Boolean primitives to full-scan production circuits. Key features of the methodology are illustrated using the energy minimization based test generation algorithm for combinational circuits. The main features of our methodology that make the test generation algorithm practical for large production circuits are: 1) only one Boolean variable is used to represent the value on a signal and all signals assume only Boolean values during the test generation procedure; 2) the function of non-Boolean primitives is separated into Boolean and non-Boolean components with energy functions required only for the Boolean component; and 3) non-Boolean components are implicitly considered in the energy minimization procedure. In this process, no new energy functions other than the normal Boolean gate energy functions are needed. We give a method for identifying and removing redundancies in production circuits using energy minimization. The formulation is also applicable to Boolean satisfiability and BDD methods. We first use the test generation algorithm for identifying undetectable faults and then relax specific constraints in the original test generation problem by ignoring the non-Boolean components. We show that undetectability in the relaxed formulation implies redundancy. We report redundancy removal results for production VLSI circuits, ISCAS 85, and full-scan versions of the ISCAS 89 benchmark circuits.

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“…The logical implications are expressed as edges. The binary relationships obtained from Equation 1 can be represented in the implication graph of directed edges as shown in Figure 1 [1,3,7]. An enhanced implication graph (EIG) was proposed by Henftling et al [18,37].…”

Section: Prior Workmentioning

confidence: 99%

“…Faultdependent techniques are mainly ATPG based methods [4,8,12,15,21,22,31,32,33,36], which target a particular fault at a time. Larrabee [23,24], starting with the Boolean difference and Chakradhar et al [5,7,9], with the neural network model, arrived at the satisfiability formulation of the ATPG problem. Both solved the problem with the help of implication graphs.…”

Section: Introductionmentioning

confidence: 99%

Using contrapositive law in an implication graph

Dave¹,

Agrawal

Bushnell

18th International Conference on VLSI Design Held Jointly With 4th International Conference on Embedded Systems Design

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Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new "oring" node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used "anding" node. An n-input gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding node graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is a set of new algorithms to update transitive closure for every newly added edge in the implication graph associated with anding and oring nodes. For the ISCAS'85 benchmark circuit c1908, the new graph identifies 5 out of a total of 7 redundant faults. The best known previous implication graph procedure could only identify 2 redundant faults. We analyze the unidentified redundant faults and suggest a possible improvement.

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Neural Models and Algorithms for Digital Testing

Cited by 42 publications

References 0 publications

A novel VLSI solution to a difficult graph problem

A novel VLSI solution to a difficult graph problem

Redundancy removal and test generation for circuits with non-Boolean primitives

Using contrapositive law in an implication graph

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