Network-on-Chip Microarchitecture-based Covert Channel in GPUs

Ahn, Jaeguk; Kim, Jiho; Kasan, Hans; Delshadtehrani, Leila; Song, Wonjun; Joshi, Ajay; Kim, John

doi:10.1145/3466752.3480093

Cited by 12 publications

(2 citation statements)

References 49 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Some studies presented covert channel-based attack models that exploit the contentions on interconnection networks inside of a GPU or communication links across multiple GPUs. Ahn et al analyzed interconnection network organizations of a modern GPU architecture to reveal the hierarchical structure of the interconnection network [37]. They disclosed attackers can design contention-based attack models since multiple SMs in the same cluster share the resource of the hierarchical interconnection structures.…”

Section: Related Work a Security Attacks On Gpumentioning

confidence: 99%

GhostLeg: Selective Memory Coalescing for Secure GPU Architecture

et al. 2022

View full text Add to dashboard Cite

Architectural considerations for secure executions are getting more critical for GPU since popular security applications and libraries have been ported to a GPU domain to rely on GPU's massively parallel computations. Recent studies disclosed the security attack models that exploit GPU's architectural vulnerabilities to leak the secret keys of AES. The attack models exploit the high correlations between the execution time of a kernel and the number of memory requests generated from memory coalescing. Thus the prior architectural defenses provide secure executions by randomizing or restricting the memory coalescing from load warps. However, those defense approaches result in significant performance overhead since memory coalescing is an essential feature for improving the performance of GPU. In this paper, we propose GhostLeg, an efficient architectural defense approach against correlation-based GPU security attacks. GhostLeg selectively applies secure executions for load warps to minimize performance overhead induced by concealing memory coalescing behavior. Our analysis of AES reveals that only the load warps whose index addresses are influenced by secret keys are vulnerable to security attacks. In order to minimize the performance overhead by secure executions, GhostLeg pinpoints the load warps that require secure executions based on the class of a source register. The secure flag assigned to each register can be set by propagation from non-deterministic user data (GhostLeg-ND) or a specific directive marked by programmers (GhostLeg-Key). Our evaluation shows that GhostLeg guarantees secure executions against the correlation-based attacks and GhostLeg-ND exhibits 54.7% higher performance compared to the stateof-the-art GPU defense solution.INDEX TERMS GPU, secure architecture, security attack, memory coalescing.

show abstract

Section: Related Work a Security Attacks On Gpumentioning

confidence: 99%

GhostLeg: Selective Memory Coalescing for Secure GPU Architecture

et al. 2022

View full text Add to dashboard Cite

show abstract

“…This research introduces an on-chip cache procedure and device that addresses the challenges associated with handling CPU and GPU access requests simultaneously. 1 However, the limited on-chip memory bandwidth often fails to meet the high bandwidth requirements of both CPUs and GPUs simultaneously, impacting the performance of both processing units. Moreover, CPUs and GPUs exhibit different memory access characteristics, which also pose distinct requirements for on-chip cache.…”

Section: Introductionmentioning

confidence: 99%

On-Chip Cache Procedure and Device for Efficient CPU and GPU Access Request Arbitration

2023

ijfans

View full text Add to dashboard Cite

This research paper presents a novel on-chip cache procedure and device that effectively handles access requests from both CPUs and GPUs. The proposed procedure involves classification caching based on the access request type, arbitrating different types of access requests for caching, and optimizing access time for CPU requests through cache while bypassing cache for GPU requests. The device includes CPU and GPU request queues, a moderator, and cache performance elements. By considering the distinct access characteristics of CPUs and GPUs simultaneously, this approach offers high performance, simple hardware implementation, and minimal cost.

show abstract