Network-on-Chip-Centric Approach to Interleaving in High Throughput Channel Decoders

Neeb, Christian; Thul, M.J.; Wehn, Norbert

doi:10.1109/iscas.2005.1464950

Cited by 37 publications

(33 citation statements)

References 15 publications

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“…Numerous methods and system architectures have been proposed to solve the memory conflict problem in a parallel turbo decoder [5,14,12,15,16,17]. However, there are several limitations of these approaches.…”

Section: B Solving Memory Conflict Problemmentioning

confidence: 99%

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Wang

Vosoughi

Shen

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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Abstract-Parallel architecture is required for high throughput turbo decoder to meet the data rate requirements of the emerging wireless communication systems. However, due to the severe memory conflict problem caused by parallel architectures, the interleaver design has become a major challenge that limits the achievable throughput. Moreover, the high complexity of the interleaver algorithm makes the parallel interleaving address generation hardware very difficult to implement. In this paper, we propose a parallel interleaver architecture that can generate multiple interleaving addresses on-the-fly. We devised a novel scheduling scheme with which we can use more efficient buffer structures to eliminate memory contention. The synthesis results show that the proposed architecture with the new scheduling scheme can significantly reduce memory usage and hardware complexity. The proposed architecture also shows great flexibility and scalability compared to prior work.

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Section: B Solving Memory Conflict Problemmentioning

confidence: 99%

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Wang

Vosoughi

Shen

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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“…Reviewing on chip permutation networks (supporting either full or partial permutation) with regard to their implementation shows that most of the networks employ a packet switching mechanism to deal with the conflict of permutated data [3]- [6]. Their implementations either use first input first output (FIFO) queues for the conflicting data [3] [5] [6] or time slot allocation in the overall system with the cost of more routing stages [5] or a complex routing with a deflection technique that avoids buffering of the conflicting data [4].…”

Section: Related Workmentioning

confidence: 99%

“…Their implementations either use first input first output (FIFO) queues for the conflicting data [3] [5] [6] or time slot allocation in the overall system with the cost of more routing stages [5] or a complex routing with a deflection technique that avoids buffering of the conflicting data [4]. The choices of network design factors, i.e., topology, switching technique and the routing algorithm, have different impacts on the on chip implementation.…”

Section: Related Workmentioning

confidence: 99%

Design and Simulation of Output Queuing with the Middle stage Buffered (OQMB) Close Packet Switching Network

Rajeshwari¹,

Bharathi²

2013

IJCA

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Clos network, a family of multistage networks, are attractive alternative for constructing scalable packet switches because of its distributed and modular design. The clos packet switching networks are the next step in scaling current crossbar switches to large number of ports. This paper presents the design and simulation of buffer less-bufferedbuffered -Clos Packet switching network architecture. This paper proposes a novel the output queuing with the middle stage buffered (OQMB) Clos Packet switching architecture that does not need any schedulers. This architecture employs an ID matching with OQMB packet switching and desynchronize static round robin (DSRR) scheme to achieve Maximum throughput under any admissible traffic. Our queuing analysis demonstrates that only small size buffers are needed in the central stage. The only trade off for the proposed (OQMB) architecture is to employ small extra resequencing buffers. Input modules with desynchronize static round robin (DSRR) scheme connection scheme guarantees no cell contention in input stages. As a result, the OQMB architecture can achieve very high performance, and high throughput under any admissible traffic.

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“…By the advances in VLSI technology, multi-processor system-on-chips with Network-on-Chip (NoC) infrastructures have been adopted to flexibly meet the requirement of computation and communication for such platforms [2,3,4,5]. One of the challenges in these NoC designs is to handle the intensive interleaving of exchanged data among the processing components [2,3,4,5]. This challenge becomes harder when the interleaving (permutation) rule, varying from one standard to another and within a single standard, even can be considered as random.…”

Section: Introductionmentioning

confidence: 99%

“…Previous work in [2] presents the parameterization (e.g., choosing buffer depth, routing algorithm, etc.) of a general-purpose 2D-mesh packet-switched network for interleaving data, rather than an optimized network design for bandwidth-/ area-efficiencies.…”

Section: Introductionmentioning

confidence: 99%

ProMINoC: An efficient Network-on-Chip design for flexible data permutation

Pham

Kim

2010

IEICE Electron. Express

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This paper presents a novel Network-on-Chip design to efficiently support data-interleaving with arbitrary permutation rule. The proposed NoC offers a run-time conflict resolution for interleaved data under arbitrary permutation rule by using a circuit-switching approach combined with a dynamic path-probing scheme. Experimental results in a 0.18 µm STD-cell CMOS process show that the proposed NoC can offer an aggregate bandwidth of up to 522.4 Gb/s, while occupying a compact area of 0.473 mm 2 (52 kGates). A comparison with other interleaving networks shows the efficiency of the proposed design.

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Network-on-Chip-Centric Approach to Interleaving in High Throughput Channel Decoders

Cited by 37 publications

References 15 publications

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

Design and Simulation of Output Queuing with the Middle stage Buffered (OQMB) Close Packet Switching Network

ProMINoC: An efficient Network-on-Chip design for flexible data permutation

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