Network flow-based simultaneous retiming and slack budgeting for low power design

Abstract

Abstract-Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design. Retiming is a procedure that involves the relocation of flip-flops (FFs) across logic gates to achieve faster clocking speed. In this paper we show that the retiming and slack budgeting problem can be formulated to a convex cost dual network flow problem. Both the theoretical analysis and experimental results show the efficiency of our approach which can not only reduce power consumption but also speedup previous work.

Improving hardware Trojan detection by retiming

“…Extra FFs can be inserted if their cost is acceptable. Other design goals such as low power and testability can also be focused during retiming [15,16]. Retiming was introduced by Leiserson and Saxe in [17].…”

“…When the vertex is selected, the corresponding edge is removed from the cycle. The vertex connected to the other side of the edge is connected to one extra zero-weight PI or PO (lines [15][16][17][18][19][20][21][22][23][24][25][26]. Weights are preserved for all edges.…”

“…Vertices which need FF insertion must propagate their requests to all their fanout paths. the CR values (lines [13][14][15][16]. As extra FFs are inserted at the outputs, the FF shifting is performed in reverse topological order (line 13).…”