a Texas Instruments, Inc.; MS 366, 13121 TI Blvd., Dallas, TX 75243 Significant sources of mechanical stress have been deliberately added into the active silicon of CMOS devices to improve carrier mobility. These include Dual Stress nitride Liners (DSL) and embedded Silicon Germanium (eSiGe) in the source and drain regions of pMOS transistors. Moreover, as transistor dimensions have shrunk, unintentional sources of variation such as Shallow Trench Isolation (STI) mechanical stress and dopant redistribution due to proximity to STI boundary or the well implant boundary (WPE) have also increased the systematic transistor variability. This increased systematic variability has impacted the product yield and provided the impetus to include context dependence in SPICE models of transistor electrical performance. This paper outlines a rigorous approach to not only quantify the physical mechanisms and impact of context effects, but also how to model these effects on the electrical transistor performance and various strategies to mitigate the impact of these context dependencies on digital circuit performance.