Degradation mechanisms of low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) under various dynamic stresses are reviewed. Dynamic hot carrier (HC) mechanism under gate and drain stress pulses is interpreted based on non-equilibrium PN junction model. For synchronized gate and drain stress pulse, both dynamic HC and self-heating (SH) mechanism are involved. For n-type TFTs, device degradation is dominated by SH at low-frequencies whereas by dynamic HC at high frequencies. Besides, for p-type TFTs, negative bias temperature instability and the dynamic HC mechanisms are both effective for the degradation.Keywords: low temperature polycrystalline silicon (LTPS), thin-film transistor (TFT), dynamic stress, non-equilibrium PN junction I. INTRODUCTION Low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) are promising candidates for realizing active-matrix display system on a panel for either LCD or OLED [1]. TFTs' device reliability is always a concern for such applications, on which previous investigations covered both direct current (dc) and alternative current (ac) stress conditions [2][3][4][5][6][7][8][9]. With no doubt, ac stress conditions are more realistic considering the actual operation conditions of TFT circuits. For MOSFETs, previous studies generally agree that the ac lifetime can be estimated based on the dc lifetime corrected by a factor larger than 1 [10]. It means that DC mechanism dominates the degradation of MOSFETs. For LTPS TFTs, although they are also field effect devices similar to MOSFETs, it will be shown that various dynamic degradation mechanisms are involved and dominate the degradation under ac stress conditions [4][5][6][7][8][9].In this paper, device degradation of LTPS TFTs under dynamic drain pluses (V d ), gate pluses (V g ), and synchronized V g /V d pulses are reviewed. The stress pulses could be positive, negative and bipolar according to the pulse base voltage (V g_b ) and its amplitude (V g_a ), as shown in Fig. 1. The degradation can be understood mainly based on a non-equilibrium PN junction degradation model, which assumes that hot carriers (HCs) will be generated in the depletion region of the non-equilibrium source/drain (S/D) junction during the voltage switching of V g , V d or both.
