Negative capacitance independent multi-gate FinFETs and their optimisations

Yang, Tingfeng; Hu, Jianping; Ni, Haiyan

doi:10.1080/00207217.2019.1584918

Cited by 4 publications

(2 citation statements)

References 12 publications

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“…Dualgate (DG) FE transistors supplement the functionality of logic circuits with tunable generators [11,12]. They also reduce the power-delay product [9,13]. Semiconductor-ferroelectricsemiconductor (SFS) wafers with a hafnia-based ultrathin buried high-k oxide (UTBOX) interlayer simplify the proposed DG FeFET planar production technology and have the potential to scale the application of ferroelectrics in microelectronics.…”

Section: Introductionmentioning

confidence: 99%

“…Semiconductor-ferroelectricsemiconductor (SFS) wafers with a hafnia-based ultrathin buried high-k oxide (UTBOX) interlayer simplify the proposed DG FeFET planar production technology and have the potential to scale the application of ferroelectrics in microelectronics. In particular, the property of FeFETs to combine the logic and memory functions simultaneously opens a way for the implementation of in-memory computing and the building novel architectures of microprocessors with a deep learning ability [13][14][15][16]. As a rule, the ferroelectric layer substitutes the conventional gate dielectric in metal oxide semiconductor field effect transistors (MOSFETs) to obtain the FeFET device structure.…”

Section: Introductionmentioning

confidence: 99%

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Robust semiconductor-on-ferroelectric structures with hafnia–zirconia–alumina UTBOX stacks compatible with CMOS technology

Popov¹,

Antonov²,

Tikhonenko³

et al. 2021

J. Phys. D: Appl. Phys.

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Silicon wafers with an ultrathin buried high-k oxide were fabricated by the atomic layer deposition of high-k layers on sapphire and silicon substrates with subsequent silicon layer transfer onto their surfaces by bonding and rapid thermal annealing (RTA). An extremely high thermal stability of hafnia orthorhombic Pca21 ferroelectric phase of up to 1100 °C was observed in the silicon-on-ferroelectric structure on the sapphire substrate. Silicon–ferroelectric–silicon structures with hafnia BOX and alumina inclusions also demonstrated increased thermal stability for hafnia or hafnia–zirconia alloys during the RTA treatment up to 900 °C, which makes them fully compatible with current complementary metal oxide semiconductor technology, promising integrated circuits for neuromorphic computation and optoelectronic switching devices.

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