Near real-time stereo range detection using a pipeline architecture

Kayaalp, Ali E.; Eckman, James L.

doi:10.1109/21.61216

Cited by 8 publications

(4 citation statements)

References 30 publications

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“…Sum of Absolute Differences (SAD) or Sum of Squared Differences (SSD), between left and right image patches evaluated along the epipolar lines. Kayaalp and Eckman [15] were one of the first to present such a system, capable of estimating disparity over a 64 disparity range in about one second for 256 × 256 images.…”

Section: Related Workmentioning

confidence: 99%

“…The first system capable of at least 30 fps -on 200 × 200 images with a 23 pixel disparity range -was on a custom platform built from off-the-shelf components by Kanade et al [16], [17]. Similarly to [15], they used a Sum of Sum of Absolute Difference (SSAD) but rather than summing over the different color channels, they summed over the six different cameras of their multi-camera system.…”

Section: Related Workmentioning

confidence: 99%

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Real-Time Dense Stereo Matching With ELAS on FPGA-Accelerated Embedded Devices

Rahnama

Frost

Mikšík

et al. 2018

IEEE Robot. Autom. Lett.

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For many applications in low-power real-time robotics, stereo cameras are the sensors of choice for depth perception as they are typically cheaper and more versatile than their active counterparts. Their biggest drawback, however, is that they do not directly sense depth maps; instead, these must be estimated through data-intensive processes. Therefore, appropriate algorithm selection plays an important role in achieving the desired performance characteristics.Motivated by applications in space and mobile robotics, we implement and evaluate an FPGA-accelerated adaptation of the ELAS algorithm. Despite offering one of the best trade-offs between efficiency and accuracy, ELAS has only been shown to run at 1.5 − 3 fps on a high-end CPU. Our system preserves all intriguing properties of the original algorithm, such as the slanted plane priors, but can achieve a frame rate of 47fps whilst consuming under 4W of power. Unlike previous FPGA based designs, we take advantage of both components on the CPU/FPGA System-on-Chip to showcase the strategy necessary to accelerate more complex and computationally diverse algorithms for such low power, real-time systems.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Real-Time Dense Stereo Matching With ELAS on FPGA-Accelerated Embedded Devices

Rahnama

Frost

Mikšík

et al. 2018

IEEE Robot. Autom. Lett.

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show abstract

“…We also assume that the derivative of p with respect to t is finite for all values of t < 0. If we filter each term of both the numerator and the denominator of equations 7 and 8 with the temporal filter, p(t), and using the commutative property of convolution again, this time in the temporal domain, we obtain: (9) and -(h®f®pt)(g ®f®p)-(g® f®p)(I' ® f®p) V -® f®p)(h ®f®p)-(gy ® f®p)(h ® I ®p) (10) where Pt 1 the derivative of the temporal filter, p. It is obvious from this equation that the selection of the temporal and spatial filters are completely independent and can be chosen separately to suit a particular application.…”

Section: Theorymentioning

confidence: 99%

“…The major problem with this type of architecture continues to be the complexity of software development. Pipelined systems, such as the SPARC[2], CYTOCOMPUTER [14], FLIP [7], CMU WARP [1], Datacube [10], and IDATEN [17,18,15], paSS the data through a number of processing elements connected in series.…”

Section: Introductionmentioning

confidence: 99%

<title>Hardware system for computing image velocity in real time</title>

et al. 1992

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A multi-purpose hardware system for processing images at video rates is described. ISHTAR (Image Sequence Hardware for Temporal Analysis in Realtime) uses 18 TI TMS32Oc4O (c40) DSP's to process input from a CCD camera or VCR source. The hardware architecture consists of a pipeline of nine processor boards, each with two c40 processors, the whole system being syrichronised by the vertical sync of the input device. This enables the calculation of a number of two dimensional convolutions to be achieved at video frame rates with a delay between the input and the output dictated by the length of the pipeline. The system is fully reconfigurable in software and partially reconfigurable in hardware so that many different types of image processing algorithms can be implemented. The specific application of a generalised gradient model to measure image motion is described, outlining the particular program structure dictated by the hardware design. The SUN 4 host has access to each processor and has the ability to change parameters and program control while the system is running. In this way active control feedback loops can be employed, particularly when the motion of the camera is under the host control, forming an active vision system. Simulations using real image sequences are presented.

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Image analysis and computer vision: 1990

Rosenfeld

1991

CVGIP: Image Understanding

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Near real-time stereo range detection using a pipeline architecture

Cited by 8 publications

References 30 publications

Real-Time Dense Stereo Matching With ELAS on FPGA-Accelerated Embedded Devices

Real-Time Dense Stereo Matching With ELAS on FPGA-Accelerated Embedded Devices

<title>Hardware system for computing image velocity in real time</title>

Image analysis and computer vision: 1990

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