Near interface traps in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

Fiorenza, Patrick; Magna, Antonino La; Vivona, Marilena; Roccaforte, Fabrizio

doi:10.1063/1.4955465

Cited by 32 publications

(23 citation statements)

References 26 publications

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“…1a) decreases with increasing the HTRB time, thus indicating the occurrence of holes trapping in the oxide layer until the hard breakdown occurs. In particular, during HTRB holes are accumulated at the SiO2/4H-SiC interface and they can be injected in the oxide via Fowler-Nordheim tunnelling [17]. After the HTRB test, the breakdown spot was identified by EMMI ( Fig.…”

Section: Methodsmentioning

confidence: 99%

“…In particular, C-AFM allowed determining the morphological shape of the surface (Fig. 4a) -a triangle with the vertex in the [11][12][13][14][15][16][17][18][19][20] direction -about 25 nm deeper than the surface of the JFET region where it is located. Even in the triangular region (highlighted with a dashed line), the surface conductivity is rather homogeneous (Fig.…”

Section: Methodsmentioning

confidence: 99%

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Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

et al. 2020

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The origin of dielectric breakdown was studied on 4H-SiC MOSFETs that failed after three months of high temperature reverse bias (HTRB) stress. A local inspection of the failed devices demonstrated the presence of a threading dislocation (TD) at the breakdown location. The nanoscale origin of the dielectric breakdown was highlighted with advanced high-spatial-resolution scanning probe microscopy (SPM) techniques. In particular, SPM revealed the conductive nature of the TD and a local increase of the minority carrier concentration close to the defect. Numerical simulations estimated a hole concentration 13 orders of magnitude larger than in the ideal 4H-SiC crystal. The hole injection in specific regions of the device explained the failure of the gate oxide under stress. In this way, the key role of the TD in the dielectric breakdown of 4H-SiC MOSFET was unambiguously demonstrated.

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Section: Methodsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

et al. 2020

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“…Many studies reported on the V th instability upon negative gate bias stress on MOSFETs [9, 52,70]. However, to get insights on the basic trapping mechanisms of NIOTs in the insulator, it is useful to analyse the behaviour of p-type MOS capacitors ( Figure 11) [71].…”

Section: Charge Trapping Phenomenamentioning

confidence: 99%

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

2019

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This paper gives an overview on some state-of-the-art characterization methods of SiO2/4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO2/SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO2/SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO2/SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO2/4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~1011 cm−2) of near interface oxide traps (NIOTs) present inside the SiO2 layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiOx layer at the interface.

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“…We discuss a possible mechanism for the improved field-effect mobility based on the excess Si atoms near the interface and interface stress during oxidation, and propose a model of the passivation mechanism. Some researchers have pointed out that near-interface oxide traps are also located close to the 4H-SiC valence band edge [20][21][22]. However, in this study, we focus on the NITs located close to the conduction band edge of 4H-SiC, which are strongly related to the channel mobility of 4H-SiC MOSFETs.…”

Section: −1mentioning

confidence: 98%

Effect of boron incorporation on slow interface traps in SiO2/4H-SiC structures

et al. 2017

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The reason for the effective removal of interface traps in SiO 2 /4H-SiC (0001) structures by boron (B) incorporation was investigated by employing lowtemperature electrical measurements. Low-temperature capacitance-voltage and thermal dielectric relaxation current measurements revealed that the density of electrons captured in slow interface traps in B-incorporated oxide is lower than that in dry and NO-annealed oxides. These results suggest that near-interface traps can be removed by B incorporation, which is considered to be an important reason for the increase in the field-effect mobility of 4H-SiC metal-oxide-semiconductor devices. A model for the passivation mechanism is proposed that takes account of stress relaxation during thermal oxidation.

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Near interface traps in SiO2/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

Cited by 32 publications

References 26 publications

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

Effect of boron incorporation on slow interface traps in SiO2/4H-SiC structures

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