Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules

Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis

“…Their approach focuses on an efficient instruction offloading technique and their framework introduces vault-level parallelism to improve computation throughput. In Reference [2] authors utilize a number of lightweight cores in conjunction with commodity two-dimensional (2D) DRAMs to explore a general-purpose NDP designs. They manage to implement an NDP execution framework that utilizes the same ISA with the host processor, and, thus, it is fully compatible with existing commercial processors.…”

“…We extend the RISC-V ISA to include the necessary functionalities to support the NDP paradigm. Processor ISA extension for NDP is also considered in Reference [2] where authors argue that such an approach provides compatibility with existing processing platforms. To this end, we implement jump-and-link-PIM (JalPim), an instruction that behaves as the original jump-andlink (Jal) instruction, and, thus, it triggers a function call.…”

“…According to the NDP premise, hardware accelerators are deployed on the DRAM die [38], which are used for accelerating code execution, while the energy costs of data transfer operations are reduced due to their spatial proximity with the DRAM [5]. NDP approaches focus on either application specific designs, such as References [41,46], or on general-purpose code execution techniques that are targeted for high-performance computer architectures, as in References [2,13,21]. Despite the fact that such designs achieve significant performance improvements, they fail to address the needs of low-power general-purpose computing that poses power and energy limitations on both architectural and circuit levels [15].…”

Design space exploration in near-data co-processors for general-purpose acceleration, in high-performance and low-power processing environments

“…In other related work [17] authors incorporate heterogeneous reconfigurable logic arrays, which behave like CGRAs in order to improve throughput and reduce the power consumption of target applications. CGRA capabilities are also explored in [18] along with different TSV interconnection networks in order to find the optimal CGRA-TSV combination that leads to the higher speedup improvement. A common target application of CGRAs and NDP is the training and inference of deep neural networks as previous works in [19] and [20] demonstrate.…”

“…On the contrary, our work does not require any profiling operation prior to code execution due to the fact that the CGRA is designed for loop acceleration and thus, it can support any issued loop without additional effort. Further, authors in [8] [16] [17] and [18] utilize CGRAs in conjunction with the NDP paradigm but their focus shifts to different aspects of the NDP execution paradigm. Under this premise, previous works lack the application mapping approach or the loop acceleration focus we employ as they do not utilize the CGRA network to execute instructions in an iterative way, i.e.…”