Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs

Yeh, Kuo-Liang; Guo, Jyh–Chyurn

doi:10.1109/ted.2012.2228196

Cited by 26 publications

(2 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1R sh is the sheet resistance of the gate material, n f is the number of fingers and the factor of 12 is due to the distributed nature of the gate resistance when it is contacted on both ends [9] [19]. However, keep reducing the transistor finger width W F or increasing number of fingers N F can result in larger gate capacitance [20]. Increase in signal quality and reduce in signal reflection is achieved with good impedance matching network.…”

Section: Methodsmentioning

confidence: 99%

Performance Analysis of Inductive Source Degeneration Low Noise Amplifier using Multi-finger Technique

Kusuma¹,

Shanthala²,

P³

2019

IJITEE

View full text Add to dashboard Cite

In the current paper, common source Low Noise Amplifier using inductively degenerated technique is designed to meet Radio Frequency (RF) range 2.45 GHz-2.85 GHz. The designed LNA is implemented using single and multi-finger transistor logic. The transistor geometry greater than 300 μm has been split into multiple fingers using multi-finger technology. The schematic is captured using ADS. The performance of LNA for various technologies has been analyzed using PTM 180 nm, PTM 130 nm and PTM 90 nm models. The amplifier with single transistor achieves minimum noise figure of 0.178 dB noise figure and maximum gain of 20.045 dB using 130 nm model technology for Bluetooth applications. Similarly 0.288 dB of minimum noise figure and peak gain of 17.971 dB are obtained using multi-finger MOSFET of PTM 90 nm technologyrespectively.The reverse isolation (S12) below -50 dB is achieved.

show abstract

Section: Methodsmentioning

confidence: 99%

Performance Analysis of Inductive Source Degeneration Low Noise Amplifier using Multi-finger Technique

Kusuma¹,

Shanthala²,

P³

2019

IJITEE

View full text Add to dashboard Cite

show abstract

“…1, where the effective total width (W T ) is the product of the number of fingers (N F ) and the width per finger (W F ). For a given W T , the device characteristics are dependent on the choice of N F and W F due to layoutdependent effects (LDEs) such as shallow trench isolation (STI) induced stress [8]- [10] and narrow width effects (NWEs) [9], [11]. As a result, the LUT of a single reference device precomputed for a specific W F and N F may be too inaccurate for computing the device parameters for arbitrary widths through linear scaling.…”

Section: Introductionmentioning

confidence: 99%

Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables

et al. 2023

View full text Add to dashboard Cite

Sizing analog circuits using precomputed look-up tables (LUTs) has recently gained traction for fast and systematic design-space exploration without a simulator in the loop. In its current form, the underlying g m /I D -based design methodology assumes that the MOSFET figures of merit are independent of absolute channel width. However, this assumption can introduce significant errors when the layoutdependent effects (LDEs) of modern CMOS technologies are considered. In this paper, an accurate and efficient procedure is developed that incorporates the dependence on the MOSFET width per finger and number of fingers in the precomputed LUTs. The proposed approach uses a set of normalized auxiliary LUTs to correct the device behavior with a subtle impact on the LUT size and the computational effort. Moreover, the nonlinear variation of the drain-to-bulk (c db ) and source-to-bulk (c sb ) capacitances with the device number of fingers is taken into account. The correction is based on precomputed simulation data and is thus independent of the model parameters and implementation. We present a track-and-hold circuit example that is sensitive to the width independence assumption, and show that the proposed fix prevents overdesign, resulting in a 44% reduction in switch area.INDEX TERMS gm/ID methodology, precomputed lookup tables, analog design automation, layout dependent effects (LDEs)

show abstract

Noise figure improvement by controlling wiring effects in RF low noise amplifiers

Jhon¹,

Jeon

Kang

2017

Microw. Opt. Technol. Lett.

View full text Add to dashboard Cite

In this letter, we evaluate the noise figure (NF) improvement that results from controlling the parasitic gate resistance of a radio‐frequency (RF) low noise amplifier (LNA). By optimizing the number of gate contacts and wiring modifications in our fabricated device, the customized layout exhibited an approximately 25% reduction in the gate electrode resistance (Relect) when compared to a reference device provided by the foundry. The fabricated LNA, which used a customized layout in a 0.18 μm standard CMOS process, improved the NF by almost 6% without affecting the Si area and DC power consumption, and exhibited a NF of 2.57 dB, gain of 11.6 dB, DC power dissipation of 4.0 mW, and return loss at both the input and output of more than 10 dB. © 2017 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:1405–1407, 2017

show abstract

Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs

Cited by 26 publications

References 16 publications

Performance Analysis of Inductive Source Degeneration Low Noise Amplifier using Multi-finger Technique

Performance Analysis of Inductive Source Degeneration Low Noise Amplifier using Multi-finger Technique

Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables

Noise figure improvement by controlling wiring effects in RF low noise amplifiers

Contact Info

Product

Resources

About