Nanowire nanocomputer as a finite-state machine

Abstract

Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each crosspoint consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future.nanocomputing | nanoprocessor | logic circuits | memory I t is widely agreed (1, 2) that because of fundamental physical limits, the microelectronics industry is approaching the end of its present Roadmap (1) for the miniaturization of computer circuits based upon lithographically fabricated bulk-silicon (Si) transistors. Therefore, much effort has been invested in the nanoelectronics field for the development of novel, alternative, nanometer-scale electronic device and fabrication technologies that could serve as potential routes for ever-denser and more capable systems to enable continued technological and economic advancement (3-17). These efforts have yielded simple nanoelectronic circuits (3)(4)(5)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17) and more complex circuit systems (6, 7) that use novel nanomaterials but are not integrated on the nanometer scale. In this regard, building a nanocomputer that transcends the ultimate scaling limitations of conventional semiconductor electronics has been a central goal of the nanoscience field and a long-term objective of the computing industry.A finite-state machine (FSM) is a representation for a nanocomputer in that it is a fundamental model for clocked, programmable logic circuits (18, 19) and integrates key arithmetic and memor...

Programmable Resistive-Switch Nanowire Transistor Logic Circuits

“…[3][4][5]19,20 To this end, we recently introduced a dielectric charge-trapping shell structure on nanowire transistor elements and showed that by modulating the charge state in the dielectric layers the transistor could be programmed as "active" or "inactive" within a specific logic window. Integration of these nanowire device elements into a crossbar array 19,20 further yielded a basic module or tile that could be used for proposed array-based architecture. 1,3−5 There are several important features critical to a programmable crossbar circuit.…”

“…Compared to charge-based programming of active/inactive nodes, 19,20 which has analogies to flash memory, 24 resistive switch elements provide potential advantages in terms of nonvolatility or retention, scaling, and programming speed and endurance. 21−23 First, in the resistive switch the state change is largely due to a local structural/ composition change in the material between switch electrodes, and the retention is often projected to be beyond years.…”

“…25 Specifically, the effective voltage on RG will be reduced from V CG in the low-R state (upper panel) to [C 1 /(C 1 + C 2 )]V CG in the high-R state (bottom panel) (see below for quantitative analysis and comparison with device experiments). The different thresholds associated with the two resistive switch states yield a hysteresis loop for transistor drain current versus V CG (Figure 1c) such that we can define a programmable logic window (gray region, Figure 1c), 1,19,20 where the resistive-switch nanowire transistor can serve as a typical transistor (red curve, "active") or as a passive resistor (blue curve, "inactive").…”

“…Each crossbar array functions as a NOR logic gate unit, and in combination can yield complete logic functions dependent only on programming and the ultimate array sizes. 3,19,20 For our demonstration, we have considered a 2-to-4 demultiplexer with active resistive switch nodes indicated by green dots; an equivalent circuit is also shown for comparison (inset, Figure 4a We fabricated the 2-to-4 demultiplexer resistive-switch nanowire transistor crossbar circuit by assembling aligned Ge/Si nanowires using nanocombing 20,39 followed by conventional lithography. 34 Figure 4b (left panel) shows a SEM image of one of the fabricated arrays consisting of 10 nanowires with 6 device nodes on each nanowire.…”

“…14,19,20 In addition, the stacked resistive switch elements (nodes in crossbar) are attractive for minimizing the area per node compared with charge-based nanowire programmable device elements. 19,20 Specifically, this study demonstrates that programming capability is maintained for a gate length of 50 nm with a 30 nm width switch element, as opposed to a >200 nm feature demonstrated in charge-based nanowire crossbar structures. 19,20 The resistive switch element does have a disadvantage compared to charge-based switches because of the additional independent RG gates required for each node.…”