Nanowire-based programmable architectures

Abstract

Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.

Two Computational Primitives for Algorithmic Self-Assembly: Copying and Counting

“…Simple examples of algorithmic self-assembly have been demonstrated, first in one-dimension 15,16 and then in two dimensions, 17 using molecular Wang tiles made of DNA. 18,19 Here we show that algorithmic self-assembly can be used to create an extended patternsbinary countingsof technological relevance for molecular electronics as the layout for a demultiplexing circuit [20][21][22][23][24] and of fundamental theoretical interest due to its appearance as a primitive for many other computation and construction tasks. [25][26][27] Additionally, using a subset of these tiles we show that a string of binary information can be propagated along the length of a DNA tube, which is of independent interest to the study of crystal evolution and the origin of life.…”

Scalability of spin field programmable gate array: A reconfigurable architecture based on spin metal-oxide-semiconductor field effect transistor

“…Here, for the first time, we report on numerical benchmark for an island-style FPGA using 22nm, 32nm and 45nm spin MOSFETs (spin FPGA) [4] by improving standard benchmark tools [6]. Compared with other proposals [7,8], spin FPGA has an advantage in that it is based on Si transistor equipping stable nonvolatile magnetic memory. Moreover, SRAM (six transistors) can be replaced by one spin MOSFET.…”

The Synthesis of Stochastic Circuits for Nanoscale Computation

“…However, we assume that these connections are nearly one-to-one, that is to say, nearly every horizontal wire connects to exactly one vertical wire, and vice-versa. This is a specific attribute of types of nanowire arrays, controlled during self-assembly (DeHon, 2005).…”

“…Existing strategies for synthesizing logic for nanowire arrays are based on routing schemes similar to those used for field-programmable gate arrays (FGPAs) (DeHon, 2005). These rely on probing the circuit and programming interconnects after fabrication.…”