Nanostructuring of Ultra-Thin HfO&lt;SUB&gt;2&lt;/SUB&gt; Layers for High-&lt;I&gt;k&lt;/I&gt;/III–V Device Application

Benedicto, Marcos; Anguita, José V.; Álvaro, Raquel; Galiana, B.; Molina-Aldereguia, J M; Tejedor, P.

doi:10.1166/jnn.2011.3498

Cited by 6 publications

(5 citation statements)

References 7 publications

(7 reference statements)

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“…The structure and surface composition of the nanopatterned HfO 2 /GaAs samples after SF 6 /Ar plasma etching were studied by highresolution transmission electron microscopy (HR-TEM) and energy-dispersive X-ray spectroscopy microanalysis (EDX) and the results will be published separately. 16)…”

Section: Sf 6 /Ar Plasma Etchmentioning

confidence: 99%

Nanoscale Selective Plasma Etching of Ultrathin HfO₂Layers on GaAs for Advanced Complementary Metal–Oxide–Semiconductor Devices

Anguita¹,

Benedicto

Álvaro³

et al. 2010

Jpn. J. Appl. Phys.

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We present a reliable dry-etch process for patterning deep-submicron structures in ultrathin (16 nm) HfO2 layers deposited on GaAs substrates. Plasma chemistries based on BCl3/O2 and SF6/Ar have been investigated using an inductively-coupled plasma reactive ion etch (ICP-RIE) reactor. The process reliability has been examined in terms of etch rate selectivity, etch time control, anisotropy, and surface roughness of the underlying GaAs substrate for potential application to gate nanopatterning in next-generation field-effect transistor fabrication. We show that a SF6/Ar plasma process provides excellent prospects as a nanopatterning method for subsequent re-growth of GaAs in novel device architectures.

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Section: Sf 6 /Ar Plasma Etchmentioning

confidence: 99%

Nanoscale Selective Plasma Etching of Ultrathin HfO₂Layers on GaAs for Advanced Complementary Metal–Oxide–Semiconductor Devices

Anguita¹,

Benedicto

Álvaro³

et al. 2010

Jpn. J. Appl. Phys.

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“…[124] Xu et al in 2018 fabricated the layered MoS 2 transistor with atomic layer deposition (ALD) HfO 2 encapsulation by chemical vapor deposition (CVD) with deep reactive ion etching (DRIE). [125][126][127] Pravin et al in 2019 developed a new numerical approach for simulating nanoscale MoS 2 -based transistor. [128] The device structure was based on MoS 2 as the channel material and SiO 2 as the gate oxide material, as shown in Figure 6d.…”

Section: Yoon Et Al In 2011 Incorporated the Performance Limit Of Mosmentioning

confidence: 99%

Sub‐5 nm 2D Semiconductor‐Based Monolayer Field‐Effect Transistor: Status and Prospects

Meena

Sharma

Jogi

2023

Physica Status Solidi (a)

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The objectives of the semiconductor industry include scaling down the silicon (Si)-based devices from bulk to nanoscale, reducing the effective cost, and improving the performance of the device. [1] Semiconductor devices such as metal-oxide semiconductor field-effect transistors (MOSFETs), field-effect transistors (FETs), complementary metal oxide semiconductor (CMOS) transistors, and other semiconductor devices with different architectures and scaling properties have been analyzed according to the guidelines of International Technology Roadmap for Semiconductors (ITRS), International Roadmap for Devices and Systems (IRDS), and Nano Electronics Roadmap for Europe: Identification and Dissemination (NEREID). Moore's law, followed for subsequent scaling down of MOSFETs, FETs, and CMOS devices using 3D semiconductors (Si, gallium nitride, and gallium arsenide), has become irrelevant in the nanoregime. [2,3] Challenges such as device degradation due to short channel effects, leakage current leading to mobility degradation, and heat dissipation issues or "heat death" of conventional 3D semiconductor-based nanodimensional CMOS devices and electronic circuits are faced due to dangling bonds, surface scattering states, undesirable coupling with phonons, creation of interface states, manifestation of the leakage current, static power problem, and large subthreshold swing (SS). [4][5][6] Search for alternate channel materials has been trending in the 2D semiconductor research in order to meet the above mentioned challenges.Richard Feynman, in 1959, introduced researchers to the concept of nanodimensions (<100 nm) and nanotechnology. The semiconductor industry has come a long way since then with newly engineered nanostructures such as carbon nanotubes (CNT), quantum dots, quantum wires, and nanofibers that have led to great advancements in nanotechnology with applications in biomedicine, pharmaceuticals, cosmetics, and environmental issues. [7] Nanomaterials are usually classified into four types based on quantum confinement and the device dimensions, at least one of which is in the nanorange (from 1 to 100 nm). Different types of nanomaterials are represented in Figure 1 and are described as follows. 1) 3D nanomaterials: The nanomaterials for which all three dimensions lie outside the nanometric scale (1-100 nm) are termed as 3D materials. The electrons are free to move in all three directions and thus there is no confinement or limitation for the flow of charge carriers. The bulk 3D nanomaterials consist of bundles of nanowires, nanotubes, bulk powders, or nanoparticles and multiple nanolayers or polycrystals. 2) 2D nanomaterials. The 2D nanomaterials have only one dimension in the nanometric scale whereas the other two dimensions lie outside the nanoscale (1-100 nm). These are similar to a planar structure. The electrons can easily move in two directions and are confined in one direction, for example, nano thin films, nanocoatings, nanolayers, nanosheets, etc. for 2D quantum well systems. 3) 1D nanomaterials: These nanoma...

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“…and below because of the thermal stability, wide band gap and high dielectric constant in MOS devices. [15][16][17][18][19] But the challenges to coat conventional polysilicon gate on HfO 2 layer are needed to be solved, such as the dopant diffusion, reaction at junction with dielectric and dopant effect. Researchers employed additional metal layer such as TiN to be compatible with high-k HfO 2 layer to fabricate the promising devices.…”

Section: Introductionmentioning

confidence: 99%

Gaussian Beam Incident on the One-Dimensional Diffraction Gratings with the High-K Metal Gate Stack Structures

Kuo¹,

Frederick²

2014

j nanosci nanotechnol

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Optical scatterometry has attracted extensive interest in extracting the geometric shape information of nanolithography patterns because of the trend of shrinking device size and complicated stack structure. RCWA is the numerical algorithm implemented in the current scatterometry tool to calculate the diffraction efficiency. However, the known weakness for the RCWA method is the analysis of metallic gratings illuminated by the TM wave. This research applies the FDTD method using the Gaussian beam excitation source to analyze the diffraction efficiency of HKMG gratings for the use in the optical scatterometry and verifies the numerical diffraction efficiency discrepancy between the Gaussian beam and plane wave excitation methods. The numerical study is carried out with the line/space nanolithography patterns on the HKMG process stacks at 45 nm node technology. The nanolithography patterns are modeled as 1-D surface relief gratings. The 0th order diffraction efficiency is analyzed as a function of CDs, SWAs, incident angles and pitches of the gratings. The study presents the impact of the polarizations of the incident waves on the diffraction efficiency. In addition, this research investigates the phase of the 0th diffraction order as a function of the SWAs and illustrates the corresponding SWA parameter effect on the phase distribution. This research suggests the minimum beam radius to converge the numerical diffraction efficiency using Gaussian beam excitation to it using the plan wave.

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Nanostructuring of Ultra-Thin HfO<SUB>2</SUB> Layers for High-<I>k</I>/III–V Device Application

Cited by 6 publications

References 7 publications

Nanoscale Selective Plasma Etching of Ultrathin HfO₂Layers on GaAs for Advanced Complementary Metal–Oxide–Semiconductor Devices

Nanoscale Selective Plasma Etching of Ultrathin HfO₂Layers on GaAs for Advanced Complementary Metal–Oxide–Semiconductor Devices

Sub‐5 nm 2D Semiconductor‐Based Monolayer Field‐Effect Transistor: Status and Prospects

Gaussian Beam Incident on the One-Dimensional Diffraction Gratings with the High-K Metal Gate Stack Structures

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Nanostructuring of Ultra-Thin HfO<SUB>2</SUB> Layers for High-<I>k</I>/III–V Device Application

Cited by 6 publications

References 7 publications

Nanoscale Selective Plasma Etching of Ultrathin HfO2Layers on GaAs for Advanced Complementary Metal–Oxide–Semiconductor Devices

Nanoscale Selective Plasma Etching of Ultrathin HfO2Layers on GaAs for Advanced Complementary Metal–Oxide–Semiconductor Devices

Sub‐5 nm 2D Semiconductor‐Based Monolayer Field‐Effect Transistor: Status and Prospects

Gaussian Beam Incident on the One-Dimensional Diffraction Gratings with the High-K Metal Gate Stack Structures

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Nanoscale Selective Plasma Etching of Ultrathin HfO₂Layers on GaAs for Advanced Complementary Metal–Oxide–Semiconductor Devices

Nanoscale Selective Plasma Etching of Ultrathin HfO₂Layers on GaAs for Advanced Complementary Metal–Oxide–Semiconductor Devices