Nanoscale TiN metal gate technology for CMOS integration

Efavi, Johnson Kwame; Mollenhauer, T.; Schmidt, M.; Gottlob, H. D. B.; Wahlbrink, T.; Kurz, H.

doi:10.1016/j.mee.2006.01.161

Cited by 37 publications

(17 citation statements)

References 7 publications

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“…This temperature dependence is related to growth of an interfacial layer for temperatures up to 900°C. Higher temperatures lead to severe reactions between TiN and Gd2O3 with a decomposition of the gate stack [13]. RTA at 800°C has therefore been chosen for dopant activation in MOSFET source/drain contacts.…”

Section: Resultsmentioning

confidence: 99%

“…Granular the replacement gate MOS capacitors have been fabricated by wet chemical removal of the Si capping layer with tetra-methyl ammonium hydroxide (TMAH). TiN Electrodes have been deposited by reactive sputtering from a Ti target with N2 addition and structured with a lift off technique [13]. MOS capacitors have been exposed to rapid thermal annealing (RTA) steps to simulate source/drain activation.…”

Section: Methodsmentioning

confidence: 99%

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Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics

Gottlob

Echtermeyer

Mollenhauer

et al. 2006

2006 European Solid-State Device Research Conference

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Two process concepts for integration of novel gate stacks with epitaxial high-K dielectrics and metal gate electrodes are presented. A "gate first" process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd2O3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a "gentle" damascene metal gate process in order to reduce process induced oxide damages.

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Section: Resultsmentioning

confidence: 99%

Section: Methodsmentioning

confidence: 99%

Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics

Gottlob

Echtermeyer

Mollenhauer

et al. 2006

2006 European Solid-State Device Research Conference

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“…Pure metal layers can be used for fabrication of nanoscale structures and rapid material screening [8], however, they suffer from mechanical stress and become unstable at temperature above 900°C [8] [9]. Thin metal layers inserted between the dielectric and standard polysilicon (MIPS), on the other hand, offer increased thermal stability and straight forward process integration of metal gates.…”

Section: Introductionmentioning

confidence: 99%

Metal gate electrodes for rare earth oxide high-k dielectrics

Schmidt

Gottlob

et al. 2009

2009 3rd International Conference on Signals, Circuits and Systems (SCS)

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A FUSI NiSi metal gate technology is used to investigate the scaling potential of high-k epitaxial gadolinium oxide (Gd 203 ) down to 0.6 nm equivalent oxide thickness. Thermally stable gate stacks have been realized by TiN electrodes on gadolinium silicate. Work function tuning of mid gap electrodes is achieved by insertion of ultrathin AIN buffer layers. Initial results based on sputtered buffer layers are transferred to atomic layer deposition technique in order to achieve atomic control of the thicknesses in combination with conformal deposition.

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“…TiN is a (conductive) metal nitride known for its high thermodynamic stability, high melting temperature (2950 ºC), high corrosion resistance and it is compatible with the CMOS fabrication processes [43,44]. It has found applications in IC technology as for example diffusion barrier [45], antireflective coating [46], gate material [47] and current conductor [48]. In MEMS, TiN is used as a heater in micro hotplates [43,49].…”

Section: Tin As Materials For Smasmentioning

confidence: 99%

“…It has a temperature coefficient of resistance (TCR) in the range of 5-20×10 -4 /ºC for sputtered films [54], while for ALD films values of 5.5×10 -4 /ºC are reported [53]. It can be patterned using wet chemical etching in a hydrogen peroxide-ammonia solution (H 2 O 2 + NH 4 OH +H 2 O [41]) or by plasma etching in a chlorine based plasma [43,47]. Both PVD and ALD TiN layers are available in the MESA+ Nanolab and can be used for the deposition of thin (100 nm) and ultra-thin (sub 10 nm) films, respectively.…”

Section: Figure 13: 'Drill-and-fill' Process For Link Fabrication: Tmentioning

confidence: 99%

Nanolink-based thermal devices : integration of ALD tin thin films

Groenland¹

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Publisher: Gildeprint Drukkerijen, Enschede MS Word thesis template by Ihor BrunetsThe cover shows an optical micrograph (topview) of Greek Cross shaped four-point structures with buried electrodes (chapter 2) for the electrical characterization of ultrathin ALD TiN layers ('Dead Cow van der Pauws') during the fabrication process after wet chemical etching of the ALD TiN layer stack, showing redeposited photoresist residues of square-shaped contact chain structures (which are located outside the image).

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Nanoscale TiN metal gate technology for CMOS integration

Cited by 37 publications

References 7 publications

Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics

Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics

Metal gate electrodes for rare earth oxide high-k dielectrics

Nanolink-based thermal devices : integration of ALD tin thin films

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