We demonstrate a vertical (3-D) gate-all-around (GAA) flash memory transistor architecture incorporating SiGe nanocrystals as floating gate on sidewalls, which can allow circumventing scaling limitations of the conventional planar flash memory transistor. These vertical devices show a large memory window, excellent retention at room temperature and at 85°C and endurance of over 105 cycles.The planar flash memory transistor cell inherently scales less aggressively compared to logic because the magnitude of the memory window is directly proportional to the gate area. Program and erase operations also apply relatively higher voltages on a flash cell, requiring a longer and heavier doped channel to prevent leakage and punch-through, as well as isolation issues. This vertical design allows scaling the memory array density beyond the aforesaid physical/dimensional limitations to facilitate higher integration density [1]. Further, while device scaling imposes the requirement of reduction in gate-stack thickness to offset short-channel-effects, thinner tunnel and control oxides lead to degraded charge retention owing to increased leakage in a continuous floating gate flash cell. Using SiGe nanocrystal quantum dots as the floating gate enables scaling the gate-stack thickness while allowing enhanced charge retention by exploiting Coulomb blockade and quantum confinement effects [2]. Finally, as the integration density of this architecture is limited only by the minimum lithographic dimension (F), approaching the theoretical maximum array density of 1/(4F2) and beyond can become possible.A gate-all-around design with sidewall channel was formed by reactive-ion etching vertical mesas out of boron doped Si (100) wafers to form the transistors with different channel lengths and gate areas. Selfaligned drain and source regions were formed by phosphorus implantation after depositing a sacrificial nitride protective layer on the sidewalls. RIE sidewall damage was cured with a sacrificial thermal oxidation step. The gate-stack included 4.5 nm of thermally grown tunnel oxide (on Si 110 surface) and 15 nm of LPCVD control oxide, while self-assembled SiGe nanocrystals 7-10 nm in diameter and with a density of-1011 cm-2 formed the floating gate. LPCVD polysilicon was then deposited, implanted and dry-etched to form the gate electrode. Electrical contacts to the drain on the top of the mesa, source at the base and gate and back-side substrate were finally formed by aluminum sputtering. While the channel material can be epitaxially grown and engineered with SiGe for enhanced hot-electron programming, this implantation process flow allows the advantage of an accessible substrate contact for body bias [3].The fabricated transistors show good transconductance and drain characteristics. While the shifting of the memory window and its closure in endurance tests require improvement, it is believed to be due to poor quality of the control oxide. In conclusion, these findings demonstrate the feasibility of ultimate scaling of the flash memory...
