Nanometer-sized etching of lithium niobate domain wall devices

Ao, Menghan; Li, Yiming; Zhong, Qilan; Cheng, Yan; Jiang, An Quan

doi:10.1016/j.ceramint.2022.10.112

Cited by 4 publications

(3 citation statements)

References 35 publications

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“…ETT is carried out on special stands under strict temperature control. The difference in the failure rate of devices in hermetic and plastic cases is explained by a greater number of cases of gate breakdown in the latter, which are more sensitive to static charges than devices in hermetic metal cases [55].…”

Section: Rejection Testsmentioning

confidence: 99%

Reliability Study of Metal-Oxide Semiconductors in Integrated Circuits

Malozyomov,

Martyushev,

Bryukhanova

et al. 2024

Micromachines

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This paper is devoted to the study of CMOS IC parameter degradation during reliability testing. The paper presents a review of literature data on the issue of the reliability of semiconductor devices and integrated circuits and the types of failures leading to the degradation of IC parameters. It describes the tests carried out on the reliability of controlled parameters of integrated circuit TPS54332, such as quiescent current, quiescent current in standby mode, resistance of the open key, and instability of the set output voltage in the whole range of input voltages and in the whole range of load currents. The calculated values of activation energies and acceleration coefficients for different test temperature regimes are given. As a result of the work done, sample rejection tests have been carried out on the TPS54332 IC under study. Experimental fail-safe tests were carried out, with subsequent analysis of the chip samples by the controlled parameter quiescent current. On the basis of the obtained experimental values, the values of activation energy and acceleration coefficient at different temperature regimes were calculated. The dependencies of activation energy and acceleration coefficient on temperature were plotted, which show that activation energy linearly increases with increasing temperature, while the acceleration coefficient, on the contrary, decreases. It was also found that the value of the calculated activation energy of the chip is 0.1 eV less than the standard value of the activation energy.

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Section: Rejection Testsmentioning

confidence: 99%

Reliability Study of Metal-Oxide Semiconductors in Integrated Circuits

Malozyomov,

Martyushev,

Bryukhanova

et al. 2024

Micromachines

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“…The dead layers at the interfaces suppress sneak current paths which otherwise can occur through persistent domain walls directly bridging metal contacts and also serve as natural embedded selectors for the cell. The mesa-structured memory cells including operation at sub-20 nm and low voltages by extending the side electrodes to the mesa surface exhibit an exceptionally high OFF–ON ratio of >10 6 with endurance over a billion cycles and show promise for the fabrication of high-density crossbar memory arrays (Figures j,k). , By extending the side electrodes to the mesa surface, energy-efficient but at the same time a fast operation of the cells could be achievedspecifically low and high currents for the write and read voltages, respectively. Erasable domain wall diodes composed of persistent and transient walls in the mesa-structured memory cells have also been utilized to realize full and half-wave rectification functionality .…”

Section: Information Storage Multilevel States and Synaptic Functiona...mentioning

confidence: 99%

Ferroelectric Domain Wall Memory and Logic

Sun,

Jiang,

Sharma

2023

ACS Appl. Electron. Mater.

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“…For the improvement, Ao et al invented a new etching technology of the LNO using CMOS-compatible SiO 2 masks, which can maintain highprecision fidelity of patterns in promoting massive production of LNO memories on the Si substrates. [76] The improved manufacturing process in high reliability is foreseeable during tailoring dual functions of storage and selector with an adjustable onset voltage. During the cell scaling study, Hu et al found the existence of a critical size depending on the strain mismatching between the LNO film and the substrate, leading to higher readout wall current and good polarization retention.…”

Section: Planar Mesa-type Dw Memorymentioning

confidence: 99%

Ferroelectric domain wall memory

Sun

Jiang

2023

Chinese Phys. B

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Ferroelectric domain walls appear as sub-nanometer-thick topological interfaces separating two adjacent domains in different orientations, and can be repetitively created, erased, and moved during programming into different logic states for the nonvolatile memory under an applied electric field, providing a new paradigm for highly miniaturized low-energy electronic devices. Under some specific conditions, the charged domain walls are conducting, differing from their insulating bulk domains. In the past decade, the emergence of atomic-layer scaling solid-state electronic devices is such demonstration, resulting in the rapid rise of domain wall nano-electronics. This review aims to the latest development of ferroelectric domain-wall memories with the presence of the challenges and opportunities and the roadmap to their future commercialization.

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Nanometer-sized etching of lithium niobate domain wall devices

Cited by 4 publications

References 35 publications

Reliability Study of Metal-Oxide Semiconductors in Integrated Circuits

Reliability Study of Metal-Oxide Semiconductors in Integrated Circuits

Ferroelectric Domain Wall Memory and Logic

Ferroelectric domain wall memory

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