Nanofloating Gate Memory Devices Based on Controlled Metallic Nanoparticle-Embedded InGaZnO TFTs

Abstract

In this letter, InGaZnO thin-film transistor (bottomgate (n+Si) and top-contact structure)-based nanofloating gate memory devices were developed. These nonvolatile transistor memory devices contained self-assembled gold nanoparticles (Au NP ) and exhibited good programmable memory characteristics according to the programming/erasing operations with large memory windows. The charge trapping in the Au NP charge storage layers was responsible for the memory operations. The good endurance and data retention capability demonstrated by these memory devices make them suitable for nonvolatile memory applications. As this approach was based on the solution-processed controlled Au NP charge trapping layers and the low-temperature synthesized transparent oxide semiconductors, it has the potential for application in low-temperature-processed transparent nonvolatile memory devices.

High-Performance Light-Erasable Memory and Real-Time Ultraviolet Detector Based on Unannealed Indium–Gallium–Zinc–Oxide Thin-Film Transistor

“…In previous reports, a-IGZO TFTs with an additional carriertrapping structure such as a floating gate [6], [7], a ferrodielectric [8], or a charge storage medium [9] memory characteristics. In this letter, a conventional a-IGZO TFT without an additional carrier-trapping structure or postannealing is proposed to serve as the memory device.…”

Nanoparticle and poly(methyl methacrylate) co-dispersion in anisole

“…The charge can be stored or erased in this layer by applying gate voltage [19]. Currently, very low concentrations of nanoparticles-typically \1 vol% in the polymer film-are used [20][21][22][23]. This low nanoparticle concentration results in a small memory capacity for these devices.…”

Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

“…Charge-trap memory thin-film transistors (CTM-TFTs) with oxide semiconductor channels have been actively investigated using various types of charge-trap (CT) materials including metal nanoparticles [1][2][3], Si-based insulators [4][5][6], high-k dielectrics [7,8], and oxide semiconductors [9,10] in an attempt to enhance the overall memory behavior. The CT layers employed in CTM-TFTs play important roles in determining the efficiency of charge-trap and de-trap events.…”