Nano Scale Dual Material Gate Silicon on Nothing Junctionless MOSFET for Improving Short Channel Effect and Analog Performance

Wagaj, S. C.; Chavan, Y. V.

doi:10.1007/978-981-10-3433-6_4

Cited by 2 publications

(1 citation statement)

References 19 publications

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“…The cut-off frequency v/s gate to source voltage characteristics of n channel different side gate length of SCDGSSONJLT and SMG SOI JLT at channel length 20nm and VDS=1V are shown in Figure 14. The cut-off frequency ƒt formula can be observed as the following equations [27][28][29] . (8) Where, Cgg is gate capacitance and gm is transconductance.…”

Section: Figure 11 Vtc For Scdgssonjlt and Scsoijlt For Channel Length 20nmmentioning

confidence: 99%

Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

Wagaj¹,

Patil²

2021

IJEAT

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In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

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Section: Figure 11 Vtc For Scdgssonjlt and Scsoijlt For Channel Length 20nmmentioning

confidence: 99%

Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

Wagaj¹,

Patil²

2021

IJEAT

View full text Add to dashboard Cite

show abstract

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

Wagaj

Patil

2019

International Journal of Electronics

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Nano Scale Dual Material Gate Silicon on Nothing Junctionless MOSFET for Improving Short Channel Effect and Analog Performance

Cited by 2 publications

References 19 publications

Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

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