Mutation-based validation of high-level microprocessor implementations

Campos, J.; Al-Asaad, Hussain

doi:10.1109/hldvt.2004.1431242

Cited by 7 publications

(5 citation statements)

References 11 publications

(5 reference statements)

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“…Camos et al [69] introduce a general description of abstract mutation based design error models that can be tailored to span any coverage measure for microprocessor validation. They then present a method of effectively using this statistical information to guide the ATPG efforts.…”

Section: Thaker Et Al Use Inmentioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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This paper starts with a comprehensive survey on RTL ATPG. It then proposes a novel RTL ATPG model based on "Gate Inherent Faults" (GIF). These GIF are extracted from each complex gate (adder, case-statement, etc.) of the RTL source code individually. They are related to the internal logic paths of a complex gate. They are not related to any net/signal in the RTL design. It is observed, that when all GIF on RTL are covered (100%) and the same stimulus is applied, then all gate level stuck-at faults of the netlist are covered (100%) as well. The proposed RTL ATPG model is therefore synthesis independent. This is shown on ITC'99 testcases. The applied semi-automatic test pattern generation process is based on functional simulation.

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Section: Thaker Et Al Use Inmentioning

confidence: 99%

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

Strauch¹

2016

Preprint

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“…The technique reduces the search space per mutant generator by selecting the signal that acts as the most common activation criteria in that cluster and designating this signal as the partitioning point. A detailed description of our "clustering and partitioning" technique can be found in [2].…”

Section: Integrating Mutant Value Generation Into the Simulation Ementioning

confidence: 99%

A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions

Campos¹,

Al-Asaad

2008

IEEE Trans. VLSI Syst.

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We present a mutation-based validation paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, design error simulation, and model-directed test vector generation. We first present a control-based coverage measure that is aimed at exposing design errors that incorrectly set control signal values. We then describe MVP's high-level concurrent design error simulator that can handle various modeled design errors. We then present fundamental techniques and data structures for analyzing high-level circuit implementations and present various optimizations to speed up the processing of data structures and consequently speed up MVP's overall test generation process. We next introduce a new automatic test vector generation technique for high-level hardware descriptions that generates a test sequence by efficiently solving constraints on multiple finite state machines. To speed up the test generation, MVP is empowered by learning abilities via profiling various aspects of the test generation process. Our experimental results show that MVP's learning abilities and automated test vector generation effectiveness make MVP significantly better than random or pseudorandom validation techniques.Index Terms-Concurrent design error simulation, design error modeling, high-level deterministic test generation, simulation-based design verification.

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“…In our previous research [1], we have defined a method to generate highly effective input stimuli by targeting the set of constraints that potentially exposes the largest number of modeled errors for any given ATPG iteration; this method, however, requires deterministic ATPG. Common high-level ATPG methods do not always perform deterministic ATPG [2] [3], and the ones that do rely on first synthesizing portions of the high-level microprocessor implementation [4].…”

Section: Introductionmentioning

confidence: 99%

“…In our previous research [1][5] [6], we have developed the methods that implement MVP (Mutationbased Validation Paradigm), our validation environment for high-level microprocessor implementations. MVP is able to handle complete implementations because it only uses high-level information, and only uses the hardware description language (HDL) information relevant to the set of constraints when identifying all relevant architectural states.…”

Section: Introductionmentioning

confidence: 99%

Simulation Data Mining for Functional Test Pattern Justification

Wen

Wang

2005

2005 Sixth International Workshop on Microprocessor Test and Verification

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Our mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP's test generation, we need to reduce the search space in the analysis process as early as possible. In this paper, we present some optimizations in the search space that speed up the overall test generation process.

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Mutation-based validation of high-level microprocessor implementations

Abstract: Abstract

Cited by 7 publications

References 11 publications

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates

A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions

Simulation Data Mining for Functional Test Pattern Justification

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