Multiword atomic read/write registers on multiprocessor systems

Larsson, Andréas; Gidenstam, Anders; Ha, Phuong Hoai; Papatriantafilou, Marina; Tsigas, Philippas

doi:10.1145/1412228.1455262

Cited by 9 publications

(24 citation statements)

References 29 publications

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“…In these contexts, the de-schedule of a lock-holding thread because of CPU-steals can lead to detrimental performance and waste of energy because of the stretch of the spin-locking phase by other threads attempting to access the same critical section. Along this direction, a lot of effort has been spent in developing non-blocking versions of classical data structures such as lists or queues [5], [6], hash-tables [7], registers [8], [9] binary-search trees [10], [11] and priority queues [12], [13]. 1 https://github.com/HPDCS/NBBS In any case, while many solutions have been devised in order to reduce the negative impact of concurrency and synchronization in memory allocation/deallocation by relying on pre-reserving or caching, no one fully faces the problem of concurrent accesses to back-end allocators.…”

Section: Related Workmentioning

confidence: 99%

A Non-blocking Buddy System for Scalable Memory Allocation on Multi-core Machines

Marotta

Ianni

Scarselli

et al. 2018

2018 IEEE International Conference on Cluster Computing (CLUSTER)

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Common implementations of core memory allocation components, like the Linux buddy system, handle concurrent allocation/release requests by synchronizing threads via spinlocks. This approach is not prone to scale with large thread counts, a problem that has been addressed in the literature by introducing layered allocation services or replicating the core allocators-the bottom most ones within the layered architecture. Both these solutions tend to reduce the pressure of actual concurrent accesses to each individual core allocator. In this article we explore an alternative approach to scalability of memory allocation/release, which can be still combined with those literature proposals. We present a fully non-blocking buddysystem, where threads performing concurrent allocations/releases do not undergo any spin-lock based synchronization. Our solution allows threads to proceed in parallel, and commit their allocations/releases unless a conflict is materialized while handling its metadata. Conflict detection relies on conventional atomic machine instructions in the Read-Modify-Write (RMW) class. Beyond improving scalability and performance, our solution can also avoid wasting clock cycles for spin-lock operations by threads that could in principle carry out their memory allocation/release in full concurrency. Thus, it is resilient to performance degradation-in face of concurrent accesses-independently of the current level of fragmentation of the handled memory blocks.

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Section: Related Workmentioning

confidence: 99%

A Non-blocking Buddy System for Scalable Memory Allocation on Multi-core Machines

Marotta

Ianni

Scarselli

et al. 2018

2018 IEEE International Conference on Cluster Computing (CLUSTER)

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“…As a consequence, we can host up to 2 32 − 2 concurrent readers, which is done by still relying on N + 2 buffers to keep the register content. Overall, compared to the work in [2], our proposal handles scenarios with a large/huge increase of the amount of threads allowed to concurrently perform read operations. Hence, we enable scaled-up wait-free concurrency on the atomic (1,N) register up to a level fitting the requirements of massively parallel applications hosted by huge (virtualized) hardware parallel platforms.…”

Section: Related Workmentioning

confidence: 99%

“…A close literature proposal based on RMW instructions, which still guarantees wait-freedom of read/write operations on (1, N) registers, is the one in [2]. However, this proposal allows up to 58 readers only on conventional 64-bit machines, while ARC can manage up to 2 32 − 2 readers, thus enabling a huge scale-up in the level of concurrency, as already hinted.…”

Section: Introductionmentioning

confidence: 99%

“…However, this proposal allows up to 58 readers only on conventional 64-bit machines, while ARC can manage up to 2 32 − 2 readers, thus enabling a huge scale-up in the level of concurrency, as already hinted. Also, the approach in [2] is based on deterministically forcing synchronization (via RMW instructions) upon any read operation, even in scenarios where the register's content has not been modified by the writer since the last read by the reader. ARC avoids executing RMW instructions in such situations, since it detects whether the last accessed snapshot of the register is still consistent (it is the most up to date one within the linearizable history of read/write accesses) by only relying on conventional memory-read machine instructions.…”

Section: Introductionmentioning

confidence: 99%

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A Wait-Free Multi-word Atomic (1,N) Register for Large-Scale Data Sharing on Multi-core Machines

Ianni

Pellegrini

Quaglia

2017

2017 IEEE International Conference on Cluster Computing (CLUSTER)

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We present a multi-word atomic (1,N) register for multi-core machines exploiting Read-Modify-Write (RMW) instructions to coordinate the writer and the readers in a wait-free manner. Our proposal, called Anonymous Readers Counting (ARC), enables large-scale data sharing by admitting up to 2 32 − 2 concurrent readers on off-the-shelf 64-bits machines, as opposed to the most advanced RMW-based approach which is limited to 58 readers. Further, ARC avoids multiple copies of the register content when accessing it-this affects classical register's algorithms based on atomic read/write operations on single words. Thus it allows for higher scalability with respect to the register size. Moreover, ARC explicitly reduces improves performance via a proper limitation of RMW instructions in case of read operations, and by supporting constant time for read operations and amortized constant time for write operations. A proof of correctness of our register algorithm is also provided, together with experimental data for a comparison with literature proposals. Beyond assessing ARC on physical platforms, we carry out as well an experimentation on virtualized infrastructures, which shows the resilience of wait-free synchronization as provided by ARC with respect to CPU-steal times, proper of more modern paradigms such as cloud computing.

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“…Peterson's construction of single-writer multi-reader (SWMR) k-word registers requires Θ(kn) SWMR single-word registers and provides Θ(kn) worst-case step complexity [21]. Using FetchAnd-Or and Swap in addition to single-word atomic registers, Larsson, Gidenstam, Ha, Papatriantafilou, and Tsigas propose a SWMR k-word atomic register implementation with Θ(kn) space complexity and Θ(k + n) worst-case step complexity [18]. In comparison, our construction (see Corollary 1) is multi-reader multi-writer (MRMW), requires Θ(kn 2 ) MRMW single-word atomic registers, and has Θ(k) worst-case step complexity (which is optimal).…”

Section: Related Workmentioning

confidence: 99%

Making objects writable

Aghazadeh

Golab

Woelfel

2014

Proceedings of the 2014 ACM Symposium on Principles of Distributed Computing

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We devise a technique for augmenting shared objects in the standard n-process shared memory model with a linearizable write() operation, using bounded space and optimal worstcase step complexity. We provide a transformation of any shared object SW supporting only sequential write() operations into an object W that supports concurrent write() operations. This transformation requires O(n 2 ) SW objects and O(n 2 ) O(log n)-bit registers, and each method (including write()) has, up to a constant additive term, the same time complexity as the corresponding method on object SW . Our implementation is deterministic, wait-free, and uses only shared registers (supporting atomic read and write operations). To the best of our knowledge, similarly efficient general constructions are not known even if stronger primitives such as CAS or LL/SC are available.Applying our transformation, we obtain an implementation of a k-word register from O(n 2 · k) single-word registers. As another application we can transform one-time TAS objects (e.g., randomized wait-free implementations that use a bounded number of registers [8,9]), into long-lived ones using also a bounded number of registers. The transformation preserves the time complexity of TAS() operations and allows resets in constant worst-case time.Our transformation employs a novel memory reclamation technique, which can replace Hazard Pointers [20] and is more efficient.

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Multiword atomic read/write registers on multiprocessor systems

Cited by 9 publications

References 29 publications

A Non-blocking Buddy System for Scalable Memory Allocation on Multi-core Machines

A Non-blocking Buddy System for Scalable Memory Allocation on Multi-core Machines

A Wait-Free Multi-word Atomic (1,N) Register for Large-Scale Data Sharing on Multi-core Machines

Making objects writable

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