Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications

Morrison, Daniel; Delic, Dennis; Yuce, Mehmet Rasit; Redouté, Jean-Michel

doi:10.1109/tvlsi.2018.2872021

Cited by 29 publications

(5 citation statements)

References 21 publications

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“…This literature recommended a D-FF design triggered by positive edge that would decrease leakage power and improve circuit performance. Chip decompression logic for analysis and the processing of compressed data are, for example, the foundation for test data compression, according to the literature on the multiple applications of LFSR in different circuit designs [11,14]. As a result, we construct route delay faults using the LFSR decompression logic.…”

Section: Development Processmentioning

confidence: 99%

High-performance LFSR circuit design based on XOR gates

Xiao

2023

J. Phys.: Conf. Ser.

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The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

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Section: Development Processmentioning

confidence: 99%

High-performance LFSR circuit design based on XOR gates

Xiao

2023

J. Phys.: Conf. Ser.

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“…Since the LFSR design is designed based on the CMOS differential buffer structure and the same clock distribution, the propagation delay in the designs gets increased. Daniel et al [26] used the LFSR circuit as a counter to reduce the decoding logic in large-scale array applications. The authors' decoding logic of the LFSR can also be implemented algorithmically to motivate high-end security.…”

Section: Related Work Of the Lfsrmentioning

confidence: 99%

“…The Mentor Graphics IC design tool is used to design the proposed LFSR circuit, and it can achieve 89.62% improvement in the power dissipation, 64.25% in the propagation delay, and 34.21% in the speed as compared to the design in [25]. Daniel et al [26] used the LFSR counter for large-scale array decoding logic and implemented using the H-spice 130 nm CMOS technology. The authors' design consumed power of 157.5 μW, which is quite high as compared to the proposed LFSR.…”

Section: Muxmentioning

confidence: 99%

Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation

Shivakumar

Senthilpari

Yusoff

2021

IJIE

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A linear feedback shift register (LFSR) has been frequently used in the Built-in Self-Test (BIST) designs for the pseudo-random test pattern generation. The higher volume of the test patterns and the lower test power consumption are the key features in the large complex designs. The motivation of this study is to generate efficient pseudo-random test patterns by the proposed LFSR and to be applied in the BIST designs. For the BIST designs, the proposed LFSR satisfied with the main strategies such as re-seeding and lesser test power consumption. However, the reseeding approach was utilized by the maximum-length pseudo-random test patterns. The objective of this paper is to propose a new LFSR circuit based on the proposed Reed-Solomon (RS) algorithm. The RS algorithm is created by considering the factors of the maximum length test patterns with a minimum distance over the time t. Also, it has been achieved an effective generation of test patterns over a stage of complexity order O (m log2 m), where m denotes the total number of message bits. We analysed our RS LFSR mathematically using the feedback polynomial function to decrease the area overhead occupied in the designs. The simulation works of the proposed RS LFSR bit-wise stages are simulated using the TSMC 130 nm on the Mentor Graphics IC design platform. Experimental results showed that the proposed LFSR achieved the effective pseudo-random test patterns with a lower test power consumption of 25.13 µW and 49.9 µs. In addition, proposed LFSR along with existing authors’ LFSR are applied in the BIST design to examine their power consumption. Ultimately, overall simulations operated with the highest operating frequency environment as 1.9 GHz.

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“…In photon counting mode, the pixel counter is reset at the start of the frame, but the SPAD front-end is set to self-rearm and outputs a pulse for every detected photon. The dedicated counter, requiring a minimal chip footprint then counts up one value after every SPAD event [4].…”

Section: Stream 2: High Speed Precision Spad Front-end Design With On-chip Photon Correlationmentioning

confidence: 99%

Microelectronic 3D Imaging and Neuromorphic Recognition for Autonomous UAVs

Zappa

Villa

Lussana

et al. 2020

NATO Science for Peace and Security Series B: Physics and Biophysics

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The article addresses the development of highly sensitive, low-light and efficient, miniature single-photon sensor technology based on Single Photon Avalanche Diode (SPAD) arrays, its integration on a Flash Light Detection and Ranging (LiDAR) system mounted on a custom built multi-rotor Unmanned Aerial System (UAS) platform, for the collection of real time imagery and performance of neuromorphic processing for accurate target detection and classification.

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Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications

Cited by 29 publications

References 21 publications

High-performance LFSR circuit design based on XOR gates

High-performance LFSR circuit design based on XOR gates

Design of a 1.9 GHz low-power LFSR Circuit using the Reed-Solomon Algorithm for Pseudo-Random Test Pattern Generation

Microelectronic 3D Imaging and Neuromorphic Recognition for Autonomous UAVs

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