Multiscan-based test compression and hardware decompression using LZ77

Wolff, Francis; Papachristou, C.

doi:10.1109/test.2002.1041776

Cited by 68 publications

(38 citation statements)

References 17 publications

(7 reference statements)

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“…In addition, the value of k is decided by the test engineer and it can be always in the range [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] (the value of k = 16 is already very high). In addition, the overhead increases linearly with k, n. Therefore, the hardware overhead of the decompressors is not expected to increase for even larger circuits than those reported in Table V.…”

Section: Comparisonsmentioning

confidence: 99%

High-Quality Statistical Test Compression With Narrow ATE Interface

Tenentes

Kavousianos

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also offers low shift switching activity and high unmodeled defect coverage at the same time. In addition, it favors multi-site testing as requires a very low pincount interface to the automatic test equipment. Finally, contrary to existing techniques, it provides an integrated solution for testing multi-core system on chips (SoCs) as it is suitable for cores of both known and unknown structures that usually coexist in SoCs.Index Terms-Defect-oriented testing, design for testability, dft, IP cores, low-power scan-based testing, multi-core SoC, selective Huffman, test data compression, unmodeled defect coverage.

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Section: Comparisonsmentioning

confidence: 99%

High-Quality Statistical Test Compression With Narrow ATE Interface

Tenentes

Kavousianos

2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…A method for encoding variable-length runs of zeroes using fixed-size blocks of encoded data was proposed in [11]. The Lempel-Ziv (LZ)-based coding methods like LZ77 [12] and LZW [13] also fall in this category. Both the LZ methods are dictionarybased methods, although the difference is in how the dictionary is formed.…”

Section: Variable-to-fixed Schemesmentioning

confidence: 99%

Relationship Between Entropy and Test Data Compression

Balakrishnan

Touba

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The entropy of a set of data is a measure of the amount of information contained in it. Entropy calculations for fully specified data have been used to get a theoretical bound on how much that data can be compressed. This paper extends the concept of entropy for incompletely specified test data (i.e., that has unspecified or don't care bits) and explores the use of entropy to show how bounds on the maximum amount of compression for a particular symbol partitioning can be calculated. The impact of different ways of partitioning the test data into symbols on entropy is studied. For a class of partitions that use fixed-length symbols, a greedy algorithm for specifying the don't cares to reduce entropy is described. It is shown to be equivalent to the minimum entropy set cover problem and thus is within an additive constant error with respect to the minimum entropy possible among all ways of specifying the don't cares. A polynomial time algorithm that can be used to approximate the calculation of entropy is described. Different test data compression techniques proposed in the literature are analyzed with respect to the entropy bounds. The limitations and advantages of certain types of test data encoding strategies are studied using entropy theory.Index Terms-Entropy theory, linear feedback shift register (LFSR) reseeding, test data compression.

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“…In 9C coding [16], an m-bit shifter is required for the decompression architecture if it drives m scan chains. In [18], the boundary scan cells need to be modified and used for decompression. Unlike FDR [3], EFDR [4], VIHC [5] and 9C coding [16], the proposed method does not require synchronization with the ATE.…”

Section: Resultsmentioning

confidence: 99%

Efficient space/time compression to reduce test data volume and testing time for IP cores

Chakrabarty

Kajihara

et al.

18th International Conference on VLSI Design Held Jointly With 4th International Conference on Embedded Systems Design

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Abstract-We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) cores. We start with a set of test cubes and use the well-known concept of scan chain compatibility to determine a small number c of tester channels that are needed to drive m scan chains (c m). Next, we exploit logic dependencies between the test data for the scan chains to design a single-level decompression circuit based on two-input gates. We refer to these procedures collectively as width (space) compression. We then determine a small set of test patterns that can provide complete fault coverage when they are applied to the circuit under test using the c tester channels; this procedure is referred to as height (time) compression. In this way, structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. The hardware overhead of the proposed approach is limited to the fan-out structure and a very small number of gates between the tester-driven external scan pins and the internal scan chains. Results are presented for the ISCAS-89 benchmarks and for four industrial circuits.

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Multiscan-based test compression and hardware decompression using LZ77

Cited by 68 publications

References 17 publications

High-Quality Statistical Test Compression With Narrow ATE Interface

High-Quality Statistical Test Compression With Narrow ATE Interface

Relationship Between Entropy and Test Data Compression

Efficient space/time compression to reduce test data volume and testing time for IP cores

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