Multiprocessor validation of the Pentium Pro

Marr, Debbie; Natarajan, S.; Thakkar, Shreekant; Zucker, Richard N.

doi:10.1109/2.544237

Cited by 8 publications

(5 citation statements)

References 8 publications

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“…A technique to evaluate peak performance has been proposed in [4], using simulation. The authors of [5] propose a validation technique based on workload models and performance tests.…”

Section: Discussionmentioning

confidence: 99%

Leveraging semi-formal and sequential equivalence techniques for multimedia SOC performance validation

Bhatia

Gaur

Tiwari

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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For multimedia SOCs supporting real time, high throughput and data intensive applications, performance validation of memory subsystems is needed to uncover the bottlenecks in the RTL implementation. Traditional validation techniques are either too slow, non-exhaustive (like performance simulations or running pseudo applications on FPGA platforms), or are not accurate enough to guarantee conformance (like abstract interpretation and analysis). In this paper we present an approach for performance validation which uses (a) semi-formal techniques rather than pure simulation for providing a wider coverage, (b) actual RTL implementations wherever available for more accurate analysis, and (c) sequential equivalence checking for validating the abstract models for IP's whose RTL is either not present or from which datapath has been abstracted out. We illustrate this approach using two case studies from video signal processing platforms. In the first study, performance issues found in silicon were detected using the proposed approach, and in the second study a number of performance bottlenecks were detected much before the RTL was frozen.

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“…A technique to evaluate peak performance has been proposed in [4], using simulation. The authors of [5] propose a validation technique based on workload models and performance tests.…”

Section: Discussionmentioning

confidence: 99%

Leveraging semi-formal and sequential equivalence techniques for multimedia SOC performance validation

Bhatia

Gaur

Tiwari

et al. 2007

Proceedings of the 44th Annual Conference on Design Automation - DAC '07

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“…Generally speaking, random simulation is the most popular validation strategy at the chip level (RTL). For example, the SPUR system [21], the SGI Challenge [6], and the recent Pentium Pro multiprocessor system [9] are validated by random simulations. …”

Section: Strategies and Resultsmentioning

confidence: 99%

“…Because all misses and all requests for dirty copies to the same cache lines are serialized either by a shared bus [6], [9] or by the directory [3], it is not difficult to understand why the memory system with a write-invalidate protocol behaves the same as the primary TSO model of Fig. 2a when the memory accesses are atomic [10].…”

Section: The S3mp Implementation Model Of Tsomentioning

confidence: 99%

Design verification of the S3.mp cache-coherent shared-memory system

Pong

Browne²,

Nowatzyk

et al. 1998

IEEE Trans. Comput.

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Abstract-This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable Shared-memory MultiProcessor (S3.mp) at three levels of abstraction: the memory consistency model, the cache coherence protocol, and the implementation.Index Terms-Cache-coherent shared-memory multiprocessors, distributed directory-based protocols, formal verification, debugging.

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“…Permissions may be requested from 1990; O' Krafka et al 1995]. Random MP test generators play pivotal roles in pre-and post-silicon validation [Marr et al 1996;Foster et al 2007;]. New and existing products boast numerous power management techniques and the most widely used standard is the Advanced Configuration and Power Interface (ACPI) specification [ACPI 2005].…”

Section: Introductionmentioning

confidence: 99%

Targeted random test generation for power-aware multicore designs

Singh

Narayanan

Landis

2012

ACM Trans. Des. Autom. Electron. Syst.

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Multicore Register Transfer Level (RTL) model simulations are indispensable in exposing subtle memory subsystem bugs. Validating memory consistency, coherency, and atomicity is a crucial design verification task. Random MultiProcessor (MP) test generators play critical roles in pre-and post-silicon validation. The Advanced Configuration and Power Interface (ACPI) standard supports dynamic frequency and voltage scaling by controlling performance states (P-States), yet multicore verification is generally conducted with cores operating at the P0-State. Independently varying core frequencies introduces new sets of intracore and intercore traffic latencies. The article introduces targeted random MP test generation techniques for multicore P-State functional verification. It develops a simple coverage metric to evaluate MP test effectiveness. The metric is demonstrated on MIP's instruction-set-based random MP tests. A novel technique is introduced to modulate the test address space by the spherical Bessel function. The technique delivers an order of magnitude coverage improvement over completely random tests. The article then outlines minimal P-State combinations to be exercised by MP tests. It also formulates two new methodologies to set up and apply MP tests for effective multicore P-State coverage. The methodologies are termed SimInit and SimTransition. First-level analyses indicate that these methods can deliver 97% to 100% improvement over random MP test coverage. ACM Reference Format:Singh, P., Narayanan, V., and Landis, D. L. 2012. Targeted random test generation for power-aware multicore designs.

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Multiprocessor validation of the Pentium Pro

Cited by 8 publications

References 8 publications

Leveraging semi-formal and sequential equivalence techniques for multimedia SOC performance validation

Leveraging semi-formal and sequential equivalence techniques for multimedia SOC performance validation

Design verification of the S3.mp cache-coherent shared-memory system

Targeted random test generation for power-aware multicore designs

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