Multiprocessor System-on-Chip (MPSoC) Technology

Wolf, Wayne; Jerraya, A.A.; Martín, Grant

doi:10.1109/tcad.2008.923415

Cited by 352 publications

(111 citation statements)

References 55 publications

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“…Figure 5 shows the relationship between the MDSU block and the neighboring blocks. The operation of the MDSU block TAP signals Stop_mode_ reg0 [1] is controlled by the extended JTAG block. The CBM module utilizes a number of the int_bkpt_en signals connected with the EA-EDU blocks and ext_bkpt_en signals connected with multiple processor cores, as shown in Fig.…”

Section: Mdsumentioning

confidence: 99%

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Easily Adaptable On-Chip Debug Architecture for Multicore Processors

Xu¹,

Park²,

Jung³

et al. 2013

ETRI J

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Jing-Zhe Xu et al. 301Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.Keywords: JTAG, on-chip debugger, on-chip debug architecture, multicore processor debugging, monitoring mode debugging. Manuscript received July 18, 2012; revised Sept. 17, 2012; accepted Oct. 1, 2012 I. IntroductionToday, the multicore processor is more attractive than the single-core processor and widely used in embedded systems. However, there are many problems that need to be solved, such as with interconnection, cache coherency, scheduling, synchronization, the programming model, application, and so on [1]- [3]. In addition to these problems, the debugging of a multicore processor is also a challenging task.Some bugs of a system on chip (SoC) or its application programs appear only when executing the applications in real cases. So, having a debug unit to support debug functions is very necessary. Because of the dramatic increase in processor performance and the intrinsic lack of observability and controllability in multicore processors, an outside debug unit can no longer provide efficient debug capabilities, for example, in-circuit emulators or ROM monitors [4], [5]. In recent years, most processors employ an on-chip debug method that embeds a debug support logic into the target processor. The on-chip debug logic embedded in a processor works by interconnecting with a software debugger. It can allow the software developer to directly control the processor operation and examine the internal status, registers, and memories for debugging.On-chip debug functionalities can be classified into three types, based on the supported debug method. The first type supports a run-stop method that stops the processor core on a desired breakpoint to inspect the core ' Developing an on-chip-based processor debugger could be a difficult and complicated job that requires considerable time and effort. Therefore, easily adaptable and flexible on-chip debug architecture is needed for small companies and academic groups that develop their own customized processor cores for ge...

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Section: Mdsumentioning

confidence: 99%

“…However, there are many problems that need to be solved, such as with interconnection, cache coherency, scheduling, synchronization, the programming model, application, and so on [1]- [3]. In addition to these problems, the debugging of a multicore processor is also a challenging task.…”

Section: Introductionmentioning

confidence: 99%

Easily Adaptable On-Chip Debug Architecture for Multicore Processors

Xu¹,

Park²,

Jung³

et al. 2013

ETRI J

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“…Therefore, in our proposed approach, we advocate an executable application model based on a well defined MoC. To specify architectural constraints, platforms are in most cases targeted towards MultiProcessor System-on-Chip (MPSoC) architectures [4]. For structural representation of such implementations, Transaction Level Modeling (TLM) is almost exclusively used today [5].…”

Section: Constraintsmentioning

confidence: 99%

A system-level synthesis approach from formal application models to generic bus-based MPSoCs

Gladigau

Gerstlauer

Haubelt

et al. 2010

2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation

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Abstract-System-level synthesis is the task of automatically implementing application models as hardware/software systems. It encompasses four basic sub tasks, namely decision making and refinement for both computation and communication. In the past, several system-level synthesis approaches have been proposed. However, it was shown that each of these approaches has drawbacks in at least one of the four sub tasks. In this paper, we present our efforts towards a comprehensive system-level synthesis by combining two academic system-level solutions into a seamless approach that automatically generates pin-accurate implementation-level models starting from a formal application model and generic MPSoC architecture templates. We analyze the system-level synthesis flow and define intermediate representations in terms of transaction level models that serve as link between existing tools. Furthermore, we present the automated transformation between models for combining two design flows. We demonstrate the combined flow on an industrial-strength example and show the benefits of fully automatic exploration and synthesis for rapid and early system-level design.

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“…In the push strategy depicted in Figure 2a, the producer first makes a write request as soon as one or more tokens have been produced (1). Then, the consumer transfers the data with a DMA (2) and sends the notification message to the producer (3).…”

Section: Solution Approachmentioning

confidence: 99%

“…One of the driving forces that motivated the emergence of multi-processor systems on chip (MPSoCs) originates from the complexity of modern applications [1]. Many applications are specified with complex block diagrams that incorporate multiple algorithms.…”

Section: Introductionmentioning

confidence: 99%

Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell

Nadezhkin

Meijer

Stefanov

et al. 2009

Lecture Notes in Computer Science

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Abstract. Kahn Process Networks (KPN) are an appealing model of computation to specify streaming applications. When a KPN has to execute on a multi-processor platform, a mapping of the KPN model to the execution platform model should mitigate all possible overhead introduced by the mismatch between primitives realizing the communication semantics of the two models. In this paper, we consider mappings of KPN specification of streaming applications onto the Cell BE multi-processor execution platform. In particular, we investigate how to realize the FIFO communication of a KPN onto the Cell BE in order to reduce the synchronization overhead. We present a solution based on token packetization and show the performance results of five different streaming applications mapped onto the Cell BE.

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Multiprocessor System-on-Chip (MPSoC) Technology

Cited by 352 publications

References 55 publications

Easily Adaptable On-Chip Debug Architecture for Multicore Processors

Easily Adaptable On-Chip Debug Architecture for Multicore Processors

A system-level synthesis approach from formal application models to generic bus-based MPSoCs

Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell

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