Multiprocessor enhancements of the SimpleScalar tool set

Manjikian, Naraig

doi:10.1145/373574.373578

Cited by 38 publications

(18 citation statements)

References 7 publications

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“…The mp_simplesim simulator [12] combined with energy analytical model is used to validate our energy optimization model. We implemented multithread SMVP running on mp_simplesim.…”

Section: Methodsmentioning

confidence: 99%

Compile-Time Energy Optimization for Parallel Applications in On-Chip Multiprocessors

Chen

Yang

et al. 2006

Computational Science – ICCS 2006

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Abstract. Energy consumption is becoming one of the key optimization objects in on-chip multiprocessor. Minimizing the energy consumption without parallel performance loss is concerned. In this paper, we focus on a DVFS-enabled onchip multiprocessor architecture, which allows dynamically adjusting each processor's voltage/frequency or shut down unused processors so to obtain energy savings. A detailed analytical model is provided and validated by experiments. Experimental results show energy saving can be up to 10.34% without performance loss.

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“…The mp_simplesim simulator [12] combined with energy analytical model is used to validate our energy optimization model. We implemented multithread SMVP running on mp_simplesim.…”

Section: Methodsmentioning

confidence: 99%

Compile-Time Energy Optimization for Parallel Applications in On-Chip Multiprocessors

Chen

Yang

et al. 2006

Computational Science – ICCS 2006

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“…In a similar vein, Naraig Manjikian [2] has stated that when using the SimpleScalar tool set on a 333-MHz Sun Ultra/10 workstation, the simulation rate was approximately 300,000 instructions/second (compared to a peak rate of over 1 billion instructions/second when executing code directly on the hardware).…”

Section: Introductionmentioning

confidence: 98%

Envelope: A New Approach to Estimating the Delivered Performance of High Performance Processors

Pressel¹

2002

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Simulating a computer run can be an excellent method for identifying performance bottlenecks and is especially valuable when discussing systems that do not yet exist. Traditional simulations collect a program trace and then have a simulator execute some subset of the trace one instruction at a time. Unfortunately, all of the standard variants of this technique are far too slow to use on jobs for high-end High Performance Computers and Supercomputers. We have developed an approach based primarily on an analysis of the memory access patterns and the number of floating point operations being executed that will estimate the performance of any run in a small fixed amount of time (e.g., a few seconds or less). Experience has shown that the results are nearly always within a factor of 2 of the measured results and frequently are within 15% or better of the measured results. u AcknowledgmentsThe author wishes to thank Csaba Zoltani and Dixie Hisley of the ARL and Punyam Satya-narayana of Raytheon for providing the necessary Perfex data.

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“…However, we do not have a proper study on performance, power and thermal issues on multicore processors since the lack of scientific applications which benefits from multicore architectures. Several researches to characterize the performance of multicore architecture have been done with multiprogramming or loop level parallel benchmark programs (Jaleel et al, 2006;Li et al, 2005;Manjikian, 2001).…”

Section: Introductionmentioning

confidence: 99%

“…Several researches have been done with SPEC to measure the performance of multicore architecture (Li et al, 2005;Manjikian, 2001 At the same time, NAS (Bailey et al, 1992) has been used to represent the workloads of scientific and engineering problems. NAS supports various versions of benchmark programs such as serial, Message Passing Interface (MPI), OpenMP and High Performance Fortran (HPF).…”

Section: Introductionmentioning

confidence: 99%

Analyzing Performance and Power of Multicore Architecture Using Multithreaded Iterative Solver

Lee¹

2010

Journal of Computer Science

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Problem statement: Scientific modeling and simulations have been popularly used with experiments and theoretical analysis in science and engineering communities. Approach: Consequently, computational demands are growing exponentially to afford large scale modeling and simulations. Results: As a result, multicore computing architectures had been proposed and several products are already available. However, we do not have a proper study on the performance, power and thermal issues of real science and engineering problems because software, which takes advantage of multicore architecture, is not available. Conclusion/Recommendations: In this study, we explored the performance and power characteristics of scientific algorithms on multicore architectures using a multithreaded version of sparse iterative linear solver, named mtCG, with real scientific application problems.

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Multiprocessor enhancements of the SimpleScalar tool set

Cited by 38 publications

References 7 publications

Compile-Time Energy Optimization for Parallel Applications in On-Chip Multiprocessors

Compile-Time Energy Optimization for Parallel Applications in On-Chip Multiprocessors

Envelope: A New Approach to Estimating the Delivered Performance of High Performance Processors

Analyzing Performance and Power of Multicore Architecture Using Multithreaded Iterative Solver

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