Multiplier Truncation in FPGA Based CWT

Qassim, Yahya T.; Cutmore, Timothy; Rowlands, D. D.

doi:10.1109/iscit.2012.6381041

Cited by 5 publications

(5 citation statements)

References 11 publications

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“…The total time elapsed in calculating the dual CWT at 133 MHz was 1.14 ms (as it was 1 ms in [18] then by scale reduction and expanding the design to analyse 2 EEGs it was 1.14 ms). The exchange between the CWT design and the WC design can be applied using the multi booting technique to solve the problem of FPGA inadequate resources.…”

Section: Resultsmentioning

confidence: 99%

“…EEG waveforms were collected from participants according to the visual oddball test by presenting one of the letters G, T, C and A as frequent stimuli on 85% of trials and the letter X randomly appeared as the oddball on 15% of trials. The recorded EEG epoch was 1400 ms (only the first 1024 ms were used for analysis as continuing to our previous works [18][19][20]). The sampling frequency was 1000 Hz for the acquired EEG and a 32-electrode cap was used according to the 10/ 20 international system [24].…”

Section: Eeg Data Acquisitionmentioning

confidence: 99%

“…Previous work by the authors has outlined the validity of WC in the ERP gamma band for finding significant relations related to cognition [17]. The involvement of the continuous wavelet transform (CWT) in analysing the EEG using FPGA and the effect of the quantization error on the produced CWT scalogram in this design with design optimizations were previously investigated by the authors [18][19][20], in which the grey blocks in Fig. 1 refer.…”

Section: Introductionmentioning

confidence: 99%

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FPGA implementation of wavelet coherence for EEG and ERP signals

Qassim

Cutmore

Rowlands

2017

Microprocessors and Microsystems

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This paper presents the design and implementation of wavelet coherence (WC) processor on low cost field-programmable gate array (FPGA). This design is adapted to estimate the wavelet coherence between two EEG signals in a minimal delay in order to support real time applications. The produced CWT coefficients were saved in static RAM chips and prepared for the WC analysis starting with the smoothing operation as an essential computation for the WC algorithm. The WC algorithm was analyzed in the means of choosing the suitable word length for the stages of the design and to simplify the employed functions in the algorithm. Several controllers that handle signal transmission among the design components were designed using hardware description language (VHDL). By using 4 parallel-processing smoothing circuits, the design is capable to calculate the coherogram between two EEG signals (1024 point each) in a total time of 128.64 ms. Image quality methods were applied for coherogram comparison between hardware and software. Hardware results were compared against the rigorous software standard WC according to the following measures; normalized mean square error (NMSE), normalized average difference (NAD) and structural content (SC) are 0.0045, 0.0485 and 0.921 respectively.

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Section: Resultsmentioning

confidence: 99%

Section: Eeg Data Acquisitionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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FPGA implementation of wavelet coherence for EEG and ERP signals

Qassim

Cutmore

Rowlands

2017

Microprocessors and Microsystems

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“…The differences between Fig. 7(a and b) are belonging to the quantization error produced during the FFT-IFFT processing and in representing the points of the signals by a finite word length (16 bit/point) in the FPGA [21].…”

Section: Discussionmentioning

confidence: 99%

“…7(a). The impact of quantization error on the results was addressed in [21] and indicated the validity of the undertaken FPGA method. …”

Section: Scale Eliminationmentioning

confidence: 99%

Optimized FPGA based continuous wavelet transform

Qassim

Cutmore

Rowlands

2016

Computers & Electrical Engineering

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a b s t r a c tA memory efficient field programmable gate array (FPGA) method is described that facilitates the processing of the continuous wavelet transform (CWT) arithmetic operations. The CWT computations were performed in Fourier space and implemented on FPGA following several optimization schemes. First, the adapted wavelet function was stored in a lookup table instead of computing the equation each time. Second, the utilization of FPGA memory was highly optimized by only storing the nonzero values of the wavelet function. This reduces 89% of the memory storage and allows fitting the entire design into the FPGA. Third, the design decreases the number of multiplications and shortens the time to produce the CWT coefficients. The proposed design was tested using EEG data and demonstrated to be suitable for extracting features from the event related potentials. Fourth, wavelet function scales were eliminated which saves further resources. The achieved computation speed allows for real time CWT application.

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Wavelet-Based Denoising of 1-D ECG Signals: Performance Evaluation

Ziani,

Rizal,

et al. 2024

Lecture Notes in Networks and Systems

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Multiplier Truncation in FPGA Based CWT

Cited by 5 publications

References 11 publications

FPGA implementation of wavelet coherence for EEG and ERP signals

FPGA implementation of wavelet coherence for EEG and ERP signals

Optimized FPGA based continuous wavelet transform

Wavelet-Based Denoising of 1-D ECG Signals: Performance Evaluation

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