Multiplier-less based architecture for variable-length FFT hardware implementation

Cuong, Nguyen Hung; Lam, Nguyen Tung; Minh, Nguyễn Đức

doi:10.1109/cce.2012.6315955

Cited by 2 publications

(1 citation statement)

References 8 publications

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“…In this paper, a 128-point FFT design is based on the architecture proposed in [14] which uses a single-delay-feedback [15] and pipeline architecture simultaneously. The 128-point FFT architecture uses mix-radix with 7 stages in which radix-2 is used for stage 7 and radix-2 2 is used for stage 1 to stage 6.…”

Section: A Fft/ifft Implementationmentioning

confidence: 99%

Hardware/software co-design of power level difference based noise cancellation

Nguyen

Dang

2015

2015 International Conference on Advanced Technologies for Communications (ATC)

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In this paper, the Power Level Difference (PLD)based noise cancelling algorithm is implemented in a Xilinx FPGA SoC using hardware/software co-design methodology. Thanks to the hardware/software co-design, the complex control part of the algorithm can be fast deployed in software meanwhile the computational part is effectively implemented in hardware. Therefore, the system can not only process the real-time input data but also consumes few hardware resource.

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Section: A Fft/ifft Implementationmentioning

confidence: 99%

Hardware/software co-design of power level difference based noise cancellation

Nguyen

Dang

2015

2015 International Conference on Advanced Technologies for Communications (ATC)

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An Efficient VLSI Implementation of OFDM based on Multiplier Less FFT & IFFT

Janani¹,

K²

2017

International Journal of Innovative Research in Electrical, Ele

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Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier system where data bits are encoded to multiple subcarriers, while being sent simultaneously. OFDM is implemented by using the combination of FFT and IFFT. The Eight point DIT-FFT & DIF IFFT architecture is implemented as a Multiplier less architecture. The eight point DIT-FFT & DIF IFFT architecture consist of two points, four points, Eight Point as Stages. The OFDM architecture was implemented based on proposed Multiplier less FFT and IFFT Block. Fast Fourier Transform is one of the important algorithms in Digital signal processing (DSP).. In this proposed method the unity gain FFTs and IFFTs without compensation circuits is implemented by using shift and add method. It reduces the amount of hardware resources of the architecture with high accuracy in calculation. This proposed method can be applied to different sizes of FFT for various designs. This approach can be Implemented using Verilog HDL and Simulated by Modelsim 6.4 c. Finally it is synthesized by Xilinx tool and Implemented in FPGA Spartan 3 XC3S 200 TQ-144.

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Multiplier-less based architecture for variable-length FFT hardware implementation

Cited by 2 publications

References 8 publications

Hardware/software co-design of power level difference based noise cancellation

Hardware/software co-design of power level difference based noise cancellation

An Efficient VLSI Implementation of OFDM based on Multiplier Less FFT & IFFT

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