Multiplier Evolution: A Family of Multiplier VLSI Implementations

Colon-Bonet, Glenn; Winterrowd, Paul

doi:10.1093/comjnl/bxm123

Cited by 11 publications

(12 citation statements)

References 6 publications

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“…The delay and design effort of this stage are highly dependent on the maximum height of the bit array. It is recognized that reduction arrays of 4:2 carry-save adders may lead to more regular layouts [16]. For instance, with a maximum height of 16, a total of 3 levels of 4:2 carry-save adders would be necessary.…”

Section: Basic Radix-16 Booth Multipliermentioning

confidence: 99%

“…For instance, for radix-16 and n-bit operands, about n/4 partial products are generated. Although less popular than radix-4, there exist industrial instances of radix-8 [10]- [16]. and radix-16 multipliers [17] in microprocessors implementations.…”

Section: Introductionmentioning

confidence: 99%

“…This extra height by a single-bit row is due to the +1 introduced in the bit array to make the two's complement of the most significant partial product (when the recoded most significant digit of the multiplier is negative). The maximum column height may determine the delay and complexity of the reduction tree [7], [16]. In [1] and [2], authors showed that this extra column of one bit could be assimilated (with just a simplified three bit addition) with the most significant part of the first partial product without increasing the critical path of the recoding and partial product generation stage.…”

Section: Introductionmentioning

confidence: 99%

“…This reduction of one bit in the maximum height might be of interest for high-performance short-bit width two's complement multipliers (small n) with tight cycle time constraints, that are very common in SIMD digital signal processing applications. Moreover, if n is a power of two, the optimization allows to use only 4-2 carry-save adders for the reduction tree, potentially leading to regular layouts [16].…”

Section: Introductionmentioning

confidence: 99%

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Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction

Antelo

Montuschi

Nannarelli

2017

IEEE Trans. Circuits Syst. I

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In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded multipliers to reduce the maximum height of the partial product columns to n/4 for n = 64-bit unsigned operands. This is in contrast to the conventional maximum height of (n + 1)/4. Therefore, a reduction of one unit in the maximum height is achieved. This reduction may add flexibility during the design of the pipelined multiplier to meet the design goals, it may allow further optimizations of the partial product array reduction stage in terms of area/delay/power and/or may allow additional addends to be included in the partial product array without increasing the delay. The method can be extended to Booth recoded radix-8 multipliers, signed multipliers, combined signed/unsigned multipliers, and other values of n.

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Section: Basic Radix-16 Booth Multipliermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction

Antelo

Montuschi

Nannarelli

2017

IEEE Trans. Circuits Syst. I

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“…As the wordlength becomes longer, the radix has been extended to radix-8 [4]- [6] and even radix-16 [7]. The advantage is that the PP reduction tree is shallower (faster and less power demanding) at expenses of a more complicate PP generation.…”

Section: Introductionmentioning

confidence: 99%

A multi-format floating-point multiplier for power-efficient operations

Nannarelli

2017

2017 30th IEEE International System-on-Chip Conference (SOCC)

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Abstract-In this work, we present a radix-16 multi-format multiplier to multiply 64-bit unsigned integer operands, doubleprecision and single-precision operands. The multiplier is sectioned in two lanes such that two single-precision multiplications can be computed in parallel. Radix-16 is chosen for the reduced number of partial products and the resulting power savings. The experimental results show that high power efficiency is obtained by issuing two single-precision multiplications per cycle. Moreover, by converting the double-precision numbers which fit to single-precision, further energy can be saved.

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Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications

Mukherjee

Ghosal

2020

Sādhanā

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Multiplier Evolution: A Family of Multiplier VLSI Implementations

Cited by 11 publications

References 6 publications

Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction

Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction

A multi-format floating-point multiplier for power-efficient operations

Low power dynamic voltage scaling and CCGDI based Radix-4 MBW multiplier using parallel HA and FA based counters for on-chip filter applications

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