Multiplexing Sense-Amplifier-Based Magnetic Flip-Flop in a 28-nm FDSOI Technology

Abstract

A novel low power non-volatile magnetic flip-flop is introduced in this paper. The perpendicular magnetic anisotropy (PMA) spin torque transfer magnetic tunnel junction (STT-MTJ) is used to design the hybrid MTJ/CMOS circuit, which is implemented with 28nm high-κ metal gate and planar ultra thin body and buried oxide (UTBB) fully depleted silicon on insulator technology (FDSOI). The proposed flip-flop structure named SA-MFF shares a sensing amplifier for normal flip-flop mode and non-volatile data sensing mode. The modified latch at output stage improves flip-flop latency. The proposed SA-MFF is symmetrical which provides equal delay for both true and complementary outputs. It can strengthen weak input signals (minimum 300 mV) and latch them to supply voltage. Forward body biasing (FBB) transistors allow for fast operation and minimum energy consumption across all modes. The proposed SA-MFF achieves 45.2 ps latency, 50.1 ps clock to output delay, 12.71 µW active power and 343.6 nW of leakage power with 1V supply voltage and 6.47 µm*4.54 µm layout area. Moreover, reliability issues are highlighted with reliability-aware simulations. Process variations of transistors/MTJs and stochastic characteristics of MTJs are investigated. Clock jitter effect and flip-flop metastability are studied.

Addressing the Thermal Issues of STT-MRAM From Compact Modeling to Design Techniques

“…Although promising, process, voltage and temperature (PVT) variations severely affect the reliability and performance of STT-MRAM as technology downscales [8]. Until now, lots of attempts have been done to address the process and voltage variations on STT-MRAM [9][10][11][12], the impact of the temperature variation or thermal fluctuation, however, has not yet been comprehensively studied. Based on our investigations, when the temperature varies, the switching current and the TMR (Tunnel magneto-resistance) ratio of the MTJ device as well as the driving capability of the CMOS access transistor fluctuate accordingly, resulting in performance and reliability degradations of STT-MRAM.…”

High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

“…MTJ with a high TMR can guarantee easy access to peripheral CMOS blocks, e.g., sensing and control circuits [28][29][30][31][32]. The real value of TMR (TMR(V)) can be adjusted by changing zero bias (TMR(0)) and V h (half of TMR (0)):…”

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology

“…In order to enhance MFF latency and reliability, we propose a modified MFF architecture with sense amplifier based flip-flop (SAFF) [20] [21]. Fig.…”